Volume 15, Issue 3 (September 2019)                   IJEEE 2019, 15(3): 310-320 | Back to browse issues page

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Razavi S M, Razavi S M. A Design Methodology for Reliable MRF-Based Logic Gates. IJEEE 2019; 15 (3) :310-320
URL: http://ijeee.iust.ac.ir/article-1-1360-en.html
Abstract:   (2810 Views)
Probabilistic-based methods have been used for designing noise tolerant circuits recently. In these methods, however, there is not any reliability mechanism that is essential for nanometer digital VLSI circuits. In this paper, we propose a novel method for designing reliable probabilistic-based logic gates. The advantage of the proposed method in comparison with previous probabilistic-based methods is its ultra-high reliability. The proposed method benefits from Markov random field (MRF) as a probabilistic framework and triple modular redundancy (TMR) as a reliability mechanism. A NAND gate is used to show the design methodology. The simulation results verify the noise immunity of the proposed MRF-based gate in the presence of noise. In addition, the values from reliability estimation program show the reliability of 0.99999999 and 0.99941316 for transistor failure rates of 0.0001 and 0.001, respectively, which are much better as compared with previous reported MRF-based designs.
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Type of Study: Research Paper | Subject: VLSI
Received: 2018/10/17 | Revised: 2019/06/04 | Accepted: 2019/02/14

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Creative Commons License This work is licensed under a Creative Commons Attribution-NonCommercial 4.0 International License.

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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.