S. Abolmaali,
Volume 18, Issue 2 (6-2022)
Abstract
In this article, a critical path identification method is proposed for ternary logic circuits. The considered structure for the ternary circuits is based on 2:1 multiplexers. Sensitization conditions for the employed ternary multiplexers are introduced. Moreover, static timing analysis and dynamic programming are utilized in the identification of true and false paths of the circuit for obtaining more realistic results in a reasonable time. An event-driven simulation engine is also developed for confirming the sensitization state of the identified paths. Some ternary arithmetic logic circuits are designed to depict the effectiveness of the proposed identification method. Simulation results show the correctness and efficiency of the proposed method.
Paramjeet ., Saptarshi Gupta, Rupali Singh,
Volume 22, Issue 2 (3-2026)
Abstract
CMOS technology, after contributing a lot to electronics world, is now facing difficulties in designing of more efficient circuits in terms of compactness, power efficiency and speed. It is happening due to various side effects being generated on account of further down scaling of feature size. The Quantum Dot Cellular Automata (QCA) technology seems to be alternate and promising technology for designing of more efficient circuits. The cryptographic encoder and decoder are the key component for secure and safe communication. This paper presents an efficient design of 1:2 demultiplexer, 1:4 demultiplexer and 4:1 multiplexer which are further used to design a cryptographic nano communication circuit. The proposed circuits are efficient in terms of energy, area and speed. The architectures are designed through multilayer approach in QCA technology that makes it compact. The efficiency of the proposed circuits has been verified through the tool QCA Designer 2.0.3.
