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Showing 2 results for Timing Analysis

S. Abolmaali,
Volume 17, Issue 3 (9-2021)
Abstract

Area reduction of a circuit is a promising solution for decreasing the power consumption and the chip cost. Timing constraints should be preserved after a delay increase of resized circuit gates to guarantee proper circuit operation. Sensitization of paths should also be considered in timing analysis of circuit to prevent pessimistic resizing of circuit gates. In this work, a greedy area reduction algorithm is proposed which is path-based and benefits well from viability analysis as the sensitization method. A proper metric based on viability conditions is presented to guide the algorithm towards selecting useful circuit nodes to be resized with acceptable performance and area reduction results. Instead of using gate slacks in resizing the candidate gates, all circuit gates are down-sized first and then the sizes of circuit gates that violate the circuit timing constraint are increased. This approach leads to considerable improvement in the complexity and performance of the proposed method. Results show that area improvement of about 88% is achievable. Comparison to a pessimistic method also reveals that on average 14.2% growth in area improvement is obtained by the presented method.

S. Abolmaali,
Volume 18, Issue 2 (6-2022)
Abstract

In this article, a critical path identification method is proposed for ternary logic circuits. The considered structure for the ternary circuits is based on 2:1 multiplexers. Sensitization conditions for the employed ternary multiplexers are introduced. Moreover, static timing analysis and dynamic programming are utilized in the identification of true and false paths of the circuit for obtaining more realistic results in a reasonable time. An event-driven simulation engine is also developed for confirming the sensitization state of the identified paths. Some ternary arithmetic logic circuits are designed to depict the effectiveness of the proposed identification method. Simulation results show the correctness and efficiency of the proposed method.


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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.