Bhagyashree Ingle, Milind Nemade,
Volume 22, Issue 0 (3-2026)
Abstract
Computing paradigm has perceived a logical shift from CPU towards application specific GPU, FPGA, CPLD due to slow down of Moore’s Law, operating system overheads, serial data processing, memory management, power efficiency and speed. The performance increase of general-purpose CPUs & GPUs is unable to match with the advances in peripheral interfaces, reconfigurable logic deployed in FPGAs provides several exceptional properties that may be able to deliver desired performance. FPGA based digital circuits provide an intermediate arrangement between ASIC and CPU with regards to through-put, latency, portability and design time. True random number generators (TRNG) are expensive, low bandwidth and speed, non-compatible with FPGA or heterogenous architectures. Therefore, design and development of alternative and affordable random-number generators is focused by several researchers. TRNG design in FPGAs is more challenging because it must meet low power and area, high speed and throughput requirements without comprising the statistical quality of the desired results for intended applications. In this paper, an attempt has been made to highlight emerging techniques and challenges associated with FPGA implementation of random number generator. Furthermore, forthcoming techniques with the use of heterogeneous computation using FPGA and python productive multiprocessor system on chip (MPSoC) architecture for generation of random numbers are discussed.
