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Showing 1 results for Euclidean Distance Calculator

E. Farshidi,
Volume 5, Issue 1 (3-2009)
Abstract

In this paper a new synthesis for circuit design of Euclidean distance calculation is presented. The circuit is implemented based on a simple two-quadrant squarer/divider block. The circuit that employs floating gate MOS (FG-MOS) transistors operating in weak inversion region, features low circuit complexity, low power (<20uW), low supply voltage (0.5V), two quadrant input current, wide dynamic range and immunity from body effect. In addition, this circuit is designed in modular methodology, leading to a very regular structure. The circuit was successfully applied to the recognition of some simple patterns. Simulation results of the circuit by HSPICE show high performance in the separation and confirm the validity of the proposed technique.

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