S. Abolmaali,
Volume 15, Issue 4 (December 2019)
Abstract
Accurate delay calculation of circuit gates is very important in timing analysis of digital circuits. Waveform shapes on the input ports of logic gates should be considered, in the characterization phase of delay calculation, to obtain accurate gate delay values. Glitches and their temporal effect on circuit gate delays should be taken into account for this purpose. However, the explosive number of combinations of waveform shapes, which can be applied to the input ports of logic gates, causes existing lookup-based methods to have huge space requirements. In this article, instead of considering all possible combinations of waveform shapes in the characterization phase of delay calculation process, the least number of combinations, which are dominant in determining the waveform shape of gate output, is presented. Multivariate Polynomial Regression (MPR) method is used to further reduce the required memory space. Exploration of the possible MPR analyses is performed to find the best regression case with proper memory space reduction and precision. Attained results show a 1.013E6 times reduction in storage space required for storing parameters utilized in extraction of output waveform characteristics in comparison to a state of the artwork, accompanied by acceptable precision.
S. Abolmaali,
Volume 17, Issue 3 (September 2021)
Abstract
Area reduction of a circuit is a promising solution for decreasing the power consumption and the chip cost. Timing constraints should be preserved after a delay increase of resized circuit gates to guarantee proper circuit operation. Sensitization of paths should also be considered in timing analysis of circuit to prevent pessimistic resizing of circuit gates. In this work, a greedy area reduction algorithm is proposed which is path-based and benefits well from viability analysis as the sensitization method. A proper metric based on viability conditions is presented to guide the algorithm towards selecting useful circuit nodes to be resized with acceptable performance and area reduction results. Instead of using gate slacks in resizing the candidate gates, all circuit gates are down-sized first and then the sizes of circuit gates that violate the circuit timing constraint are increased. This approach leads to considerable improvement in the complexity and performance of the proposed method. Results show that area improvement of about 88% is achievable. Comparison to a pessimistic method also reveals that on average 14.2% growth in area improvement is obtained by the presented method.
S. Abolmaali,
Volume 18, Issue 2 (June 2022)
Abstract
In this article, a critical path identification method is proposed for ternary logic circuits. The considered structure for the ternary circuits is based on 2:1 multiplexers. Sensitization conditions for the employed ternary multiplexers are introduced. Moreover, static timing analysis and dynamic programming are utilized in the identification of true and false paths of the circuit for obtaining more realistic results in a reasonable time. An event-driven simulation engine is also developed for confirming the sensitization state of the identified paths. Some ternary arithmetic logic circuits are designed to depict the effectiveness of the proposed identification method. Simulation results show the correctness and efficiency of the proposed method.
Elahe Rezaee Ahvanooii, Sheis Abolmaali,
Volume 21, Issue 3 (September 2025)
Abstract
Touch, one of the fundamental human senses, is essential for understanding the environment by enabling object identification and stable movements. This ability has inspired significant advancements in artificial neural networks for object recognition, texture identification, and slip detection applications. However, despite their remarkable capacity to simulate tactile perception, artificial neural networks consume considerable energy, limiting their broader adoption. Recent developments in electronic skin technology have brought robots closer to achieving human-like tactile perception by enabling asynchronous responses to temperature and pressure changes, thereby enhancing robotic precision in tasks like object manipulation and grasping. This research presents a Spiking Graph Convolutional Network (SGCN) designed for processing tactile data in object recognition tasks. The model addresses the redundancy in spiking-format input data by employing two key techniques: (1) data compression to reduce the input size and (2) batch normalization to standardize the data. Experimental results demonstrated a 93.75% accuracy on the EvTouch-Objects dataset, reflecting a 4.31% improvement, and a 78.33% accuracy on the EvTouch-Containers dataset, representing an 18% improvement. These results underscore the SGCN's effectiveness in reducing data redundancy, decreasing required time steps, and optimizing tactile data processing to enhance robotic performance in object recognition.
