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Showing 20 results for Subject: Analog Circuits

H. Miar- Naimi, M. Zabihi,
Volume 5, Issue 4 (12-2009)
Abstract

Abstract— This paper presents a novel approach to obtain fast locking PLL by embedding a nonlinear element in the loop of PLL. The nonlinear element has a general parametric Taylor expansion. Using genetic algorithm (GA) we try to optimize the nonlinear element parameters. Embedding optimized nonlinear element in the loop shows enhancements in speed and stability of PLL. To evaluate the performance of the proposed structure, various tests performed and results compared with standard phase locked loop. The tests and results show the superior performance of the proposed PLL.
S. H Mirhosseini, A. Ayatollahi,
Volume 6, Issue 4 (12-2010)
Abstract

Abstract- A novel low-voltage two-stage operational amplifier employing resistive biasing is presented. This amplifier implements neutralization and correction common mode stability in second stage while employs capacitive dc level shifter and coupling between two stages. The structure reduces the power consumption and increases output voltage swing. The compensation is performed by simple miller method. For each stage an independent common-mode feedback circuits has been used. Simulation results show that power consumption is 2.1 mW at 1V supply. The dc gain of the amplifier is about 70 dB while its output swing is as high as around 1.2V.
H. Faraji Baghtash, S. J. Azhari, Kh. Monfaredi,
Volume 7, Issue 4 (12-2011)
Abstract

In this paper a novel very high performance current mirror is presented. It favorably benefits from such excellent parameters as: Ultra high output resistance (36.9GΩ), extremely low input resistance (0.0058Ω), low output (~0.18V) and low input voltage (~0.18V) operation, very low power consumption (20μW), very low offset current (1pA), ultra wide current dynamic range (150dB), and ultra high accuracy (error = 0.003%). The circuit has a very simple compact architecture and uses a single 1V power supply. The qualitative performance of the circuit is validated with HSPICE simulations using HSPICE TSMC 0.18μm CMOS technology.
M. Rafei, M. R. Mosavi,
Volume 8, Issue 2 (6-2012)
Abstract

One of the most important features of the Active Inductors (AIs) is their input equivalent resistance, namely series-loss resistance, which should be low enough to have a high Quality Factor (QF). Most of the previous methods by this goal did not yield a high enough QF. This paper presents a new method, namely applying an RC feedback, to cancel series-loss resistance entirely. As the RC feedback cancels series-loss resistance, it enhances the Self-Resonant Frequency (SRF) as well. The SRF of the AI has a range as high as 0.25-12.5 GHz. Compared to the previous reports, the QF has been improved by applying the RC feedback. The structure is such that the QF can be adjusted independent of the SRF. For example, a very high quality factor of 13159 at the frequency of 6.6 GHz with a 2.2 nH inductance is obtained, while noise voltage and power dissipation are less than 4.6 nV Hz and 4 mW, respectively. The AI is designed and simulated using 90 nm CMOS process and 1.2 V power supply. To the best of authors’ knowledge, this is the first time an RC feedback has been implemented to cancel series-loss resistance.
A. Roohavar, S. J. Azhari,
Volume 11, Issue 4 (12-2015)
Abstract

this paper presents a novel fully differential (FD) ultra high common mode rejection ratio (CMRR) current operational amplifier (COA) with very low input impedance. Its FD structure that attenuates common mode signals over all stages grants ultra high CMRR and power supply rejection ratio (PSRR) that makes it suitable for mixed mode and accurate applications. Its performance is verified by HSPICE simulations using TSMC 0.18µm CMOS technology and ±0.75V supply voltage that indicate such outstanding results of 81.1dB gain,298MHz gain-bandwidth product, 64º phase margin, 28.2m&Omega input impedance, 159dB CMRR and PSRR+/PSRR- of 174dB/163dB all at low power consumption of 0.302mW.To study the robustness of the COA against technology and get such results close to measurement, Monte Carlo analysis is applied on both pre- layout and post layout simulations of the design. The results are as 73.29dB and 2.07MHz, 1.92&Omega, and150.35dB for Ai magnitude and bandwidth, Ri, and CMRR, respectively, in pre-layout case while change to 66.58dB and 1.44 MHz, 11.07 &Omega, and 147.10dB, for the same arrange, in post layout case. These measurement-like results thus, prove excellent practical performance of the proposed COA.

AWT IMAGE


Dr B Chaturvedi, Dr J Mohan,
Volume 11, Issue 4 (12-2015)
Abstract

In this paper, a new voltage controlled first order all-pass filter is presented. The proposed circuit employs a single differential voltage dual-X second generation current conveyor (DV-DXCCII) and a grounded capacitor only. The proposed all-pass filter provides both inverting and non inverting voltage-mode outputs from the same configuration simultaneously without any matching condition. Non-ideal analysis along with sensitivity analysis is also investigated. The proposed circuit has low active and passive sensitivities. As an application the proposed all-pass filter is connected in cascade to get higher order filter. The theoretical results are validated thorough PSPICE simulations using TSMC 0.18µm CMOS process parameters.

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M. Safari, M. Eghtesadi, M. R. Mosavi,
Volume 12, Issue 2 (6-2016)
Abstract

In this paper, a new design of concurrent dual-band Low Noise Amplifier (LNA) for multi-band single-channel Global Navigation Satellite System (GNSS) receivers is proposed. This new structure is able to operate concurrently at frequency of 1.2 and 1.57 GHz. Parallel and series resonance parts are employed in the input matching in order to achieve concurrent performance. With respect to used pseudo-differential structure, LNA is basically a single-ended-to-differential conversion and it consequently has no need to balun. In addition, an inductively degenerated cascode approach is employed to have better simultaneous matching and Noise Figure (NF). Simulations are performed with TSMC  0.18 μm technology in ADS software. Results analysis present that LNA achieves input matchings of -11.024 and -13.131 dB, NFs of 2.315 and 2.333 dB, gains of 26.926 and 27.576 dB, P-1dB of -15.3 and -13 dBm, IIP3 of -0.9 and 2.2 dBm at 1.2 and 1.57 GHz, respectively. Besides, LNA consumes 8.32 mA DC current from a 1.8 V supply voltage.


T. Azadmousavi, H. Faraji Baghtash, E. Najafi Aghdam,
Volume 15, Issue 2 (6-2019)
Abstract

A power efficient gain adjustment technique is described to realize programmable gain current mirror. The dissipation power changes over the wide gain range of structure are almost negligible. This property is in fact very interesting from power management perspective, especially in analog designs. The simple structure and constant frequency bandwidth are other ever-interesting merits of proposed structure. The programming gain range of structure is from zero up to 18dB under operating frequency range from 72 kHz to 173 MHz. The maximum power dissipation of designed circuit is only 3.1 µW which is drawn from 0.7 V supply voltage. Simulation results in 0.18 µm CMOS TSMC standard technology demonstrate the high performance of the proposed structure.

M. Srivastava, K. Bhardwaj,
Volume 15, Issue 3 (9-2019)
Abstract

In this paper two R‑L network simulator configurations employing a single VDDIBA, one resistance and one grounded capacitance are presented. The first configuration is a grounded series resistor-inductor (R‑L) network simulator and the second configuration is intended for grounded parallel resister-inductor (R‑L) circuit simulation. Both the proposed circuits enjoy several beneficial features such as: 1) compact structure employing only one VDDIBA and two passive elements, 2) electronic tuning of inductive part of realized series/parallel R‑L impedances, 3) independent control of inductive and resistive parts of realized parallel R‑L impedance, 4) no requirement of any component matching, and 5) un-deviated performance in non-ideal environment. By choosing appropriate values of active/passive elements, a series R‑L circuit for simulating resistance of 7.742 kΩ and inductance of value 7.742 mH has been developed. Similarly a parallel R‑L simulation circuit to simulate a resistance of value 1 kΩ and inductance of value 77.4 µH is implemented. To study the influence of parasitics on developed lossy inductances, the behavior of these configurations has been studied keeping terminal parasitics of VDDIBAs under consideration. To check the performance and usefulness of the proposed configurations some second-order filtering circuits have been designed. To confirm the theoretical analysis, PSPICE Simulation results have been included.

H. Faraji Baghtash, Kh. Monfaredi,
Volume 15, Issue 3 (9-2019)
Abstract

A novel active feedback frequency compensation scheme is presented in this work. Based on the proposed technique, an amplifier with two main poles in its frequency bandwidth can be easily compensated by introducing a pole-zero pair in a local feedback. The proposed method is mathematically analyzed and then based on the derived formulations, a design procedure is established. The capability of the proposed technique is examined considering a well-known two-stage amplifier, considering just a trivial modification on its input stage. To gain an analogous and fair insight, the performance of the proposed structure is compared with that is of the optimally designed miller-compensated two-stage amplifier. The post-layout simulations are accomplished with TSMC 180nm CMOS standard technology. The Spectre post-layout simulations show that the proposed structure outperforms the traditional structure in terms of power consumption and gain bandwidth product. The robustness of the design is checked with Monte Carlo simulations.

T. S. Arora,
Volume 16, Issue 2 (6-2020)
Abstract

Realization of a novel single-resistance-controlled oscillator, employing an active element and all grounded passive elements, is the purpose of this manuscript. With requirements for completing the design being only a single Voltage Differencing Current Conveyor and four grounded passive components, it is also a preferable choice for integrated circuit implementation. The designed circuit has an independent control of the frequency of oscillation and current mode output can be achieved from high impedance port, explicitly. Simulation results are presented using PSPICE software along with the regular mathematical analysis. At last experimental verification of the proposed circuit is shown using commercially available integrated circuits.

P. Gupta, S. K. Jana,
Volume 17, Issue 2 (6-2021)
Abstract

The advancement in the integrated circuit design has developed the demand for low voltage portable analog devices in the market. This demand has increased the requirement of the low-power RF transceiver. A low-power phase lock loop (PLL) is always desirable to fulfill the need for a low power RF transceiver. This paper deals with the designing of the low power transconductance- capacitance (Gm-C) based loop filter with the help of the gate-driven quasi bloating Bulk (GD-QFB) MOS technique. The GD-QFB MOS-based operational transconductance amplifier (OTA) has been proposed with a high dc gain of 82.41 dB and less power consumption of 188.72 µW. Further, Gm-C based active filter has been designed with the help of the proposed GD-QFB OTA. The simulation results of Gm-C filter attain a -3 dB cut-off frequency of 59.08 MHz and power consumption of 188.31µW at the supply voltage of 1V. The proposed Gm-C filter is suitable for the designing of 1-3 GHz low power PLL.

N. Raj,
Volume 17, Issue 3 (9-2021)
Abstract

The performance of any system is decided by the circuit configurations used in its implementation. Current mirror is one of those circuit configurations which are widely used in analog system designs. The performance of current mirror is decided by its parameters which include large operating range, wide bandwidth along with very low input and very high output resistances. In this paper, a low voltage flipped voltage follower based current mirror is presented. The structure flipped voltage follower is initially modified using a feedback path which results in the low impedance node which when considered as input in the proposed current mirror results in an extremely low value of input resistance. Compared to conventional flipped voltage follower based current mirror design the proposed design works well with minimum error in microamperes range with extended bandwidth without affecting its output resistance. The input resistance gets scaled down to 17 ohms from 840 ohms whereas bandwidth gets almost doubled approximately to 4.5GHz from 2.4GHz. The power dissipation ranges in microwatts. The simulations are supported with mathematical analysis. The complete analysis is done in HSpice using MOS models of 0.18-micron technology at a dual supply voltage, ±0.5V.

H. Ghonoodi, M. Hadjmohammadi,
Volume 17, Issue 4 (12-2021)
Abstract

In this paper a novel design is presented for a dual-band LC oscillator, using an analytical approach. The core of the proposed circuit contains a cross-coupled CMOS LC oscillator with two serried LC tanks so that the inductors of these tanks have mutual inductance. There are some switches in the circuit that directly changes mutual inductance to produce two different frequencies. This technique increases the oscillation amplitude in the same power consumption that leads to the decrement of phase noise. In other words, using two serried LC tank compensates the injected phase noise from switches. The symmetrical structure is another advantage of the presented design that makes it possible to be used in multiphase oscillator. To assess the quality of the proposed circuit, a dual-band quadrature LC oscillator has been designed to oscillate at 3.6 GHz and 6.4 GHz with 1.5 V supply and 1 mA current consumption, with TSMC 0.18 CMOS practical model. Lastly, simulation results confirm the correctness of analytical results and high proficiency of the proposed design.

G. Vasudeva, B. V. Uma,
Volume 18, Issue 3 (9-2022)
Abstract

Successive approximation register (SAR) analog to digital converter (ADC) architecture comprises submodules such as comparator, digital to analog converters (DAC), and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements, and ADC metrics are presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two-stage segmented resistive string DAC architecture, and low power SAR logic are designed and integrated to form the ADC architecture with a maximum sampling rate of 1 GS/s. Circuit schematic is captured in cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC are evaluated in MATLAB environment. Differential nonlinearity and integral nonlinearity metrics for the 12-bit ADC are limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency up to 1 GSps is designed in this work with low power dissipation of less than 10 mW.

B. Dorostkar Yaghouti,
Volume 19, Issue 2 (6-2023)
Abstract

 By increasing the transceiver devices within the 3.1 to 10.6 GHz frequency band, the interferers and strong blockers from different equipment degraded the main received signals, so linearity performance becomes more notable. In this paper, a two-path low noise amplifier (LNA) is proposed for satisfying the overall efficiency of the Ultra-wideband (UWB) radar used in vital sign detection, precise indoor localization, and high data rate wireless communications. A novel high linear circuit is recommended based on Complementary Derivative Superposition (CDS) and Post Distortion (PD) techniques. High pass filter and inductive source degeneration structured input impedance matching. Post layout results of the designed UWB-LNA in 180-nm CMOS represented the average of third-order Intercept Point (IIP3) is 8.1 dBm, S21 is 11 dB and, S11 is below -10 dB. The minimum noise figure (NF) is 3.11 dB. The circuit draws 12.7 mA at 1.4-V. The chip area is 930 µm × 1090 µm. The proposed design in this work exhibits higher FOM compared to similar LNAs, It is clear, high-linearity performance in total bandwidth is an advantage compared to recent articles.

Ananthakrishna T, Guru Prasad, A. Gopalkrishna Pai ,
Volume 19, Issue 3 (9-2023)
Abstract

This paper presents a low dropout voltage regulator, with the specifications suitable for hearing aid devices. The proposed LDO occupies very less area on chip and provides an excellent transient response. A novel voltage spike suppressor block is employed in the LDO architecture which reduces undershoot and overshoot of the output voltage during the abrupt load transition. It introduces a secondary negative feedback loop whose delay is lesser than the main loop and also steers the quiescent current to output node when required. This not only improves overall current efficiency but also reduces the on chip capacitance. The proposed LDO is laid out in 180 nm standard CMOS technology and post layout simulations are carried out. The LDO produces 0.9 V output when a minimum supply voltage of 1 V is applied. A maximum load of 0.5 mA can be driven by the regulator. The LDO exhibits 4.4 mV/V and 800 μV/mA line and load regulations respectively. When subjected to a step load change, an undershoot of 20.34 mV and an overshoot of 30.28 mV are recorded. For proper operation of the LDO, it requires only 4.5 pF on-chip capacitance.

Maryam Akbari, Sattar Mirzakuchaki, Mahdi Fazeli, Mohammad Reza Tarihi,
Volume 19, Issue 4 (12-2023)
Abstract

In light of the growing prevalence of Internet of Things (IoT) devices, it has become essential to incorporate cryptographic protection techniques for high-security applications. Since IoT devices are resource-constraints in terms of power and area, finding cost-effective ways to enhance their security is necessary. Physical unclonable function (PUF) is considered a trusted hardware security mechanism that generates true and intrinsic randomness by extracting the inherent process variations of circuits. In this paper, a novel pure magnetic memory-based PUF is presented. The fundamental building blocks of the proposed PUF design are magnetic devices, the so-called mCells. These magnetoresistive devices exclusively utilize Magnetic Tunnel Junction (MTJ) components. Using purely MTJ in the main memory and sense amplifier in the proposed PUF leads to high randomness, high reliability, low power, and ultra-compact occupation area. The Monte Carlo HSPICE simulation results demonstrate that the proposed PUF achieves a uniqueness of 49.89%, uniformity of 50.02 %, power consumption of 1.43 µW, and an area occupation of 0.01 µm2 per bit.
Arsen Ahmed, Hüseyin Demirel,
Volume 19, Issue 4 (12-2023)
Abstract

In the past twenty years, low-voltage and power design have gained attention in analog VLSI design, particularly for high-performance and portable integrated circuits (ICs). Because of the increasing density of large-scale integration, a single silicon A.S.I. chip could have thousands or even millions of transistors on it. A rise in integration levels led to the development of Fin-type Field Effect Transistor (FinFETs) technology. In this research, an improved circuit design for a floating active inductor (FAI) and quadrature sinusoidal oscillator (QSO) is implemented employing only two active filters, the Z-copy-Voltage Differential Transimpedance Amplifier (Zc-VDTA). The purpose of the FAI is to contain two Zc-VDTA and one resistor with a ground capacitor, and it is easy to integrate the parameters of the Zc-VDTA bias current (IB) through the adjustment of the circuit. In order to verify the dependability of the circuits designed using floating active inductance circuits, a Butterworth fourth-order low-pass filter was created via component replacement. All the simulations have been carried out on 7 nm using linear technology SPICE, and cadence virtuoso tool.
Chhaya Belwal, Kunwar Singh, Shireesh Kumar Rai,
Volume 20, Issue 2 (6-2024)
Abstract

This paper introduces a floating flux-controlled meminductor emulator, implemented using two voltage differencing differential difference amplifier (VDDDA) along with a memristor and capacitor. Grounded and floating configurations are simulated with TSMC 0.18 µm level-49 BSIM3 CMOS process parameters in LTspice, showcasing the performance of the proposed circuits. The circuit features electronic tunability, allowing for the adjustment of nonlinear flux through the tuning of bias voltage. Simulation results validate the frequency-dependent current-flux dynamics of the proposed meminductor emulator. The simulation results, which involve frequency-dependent pinched hysteresis loops, transient analysis, non-volatility, and Monte Carlo analysis of the proposed meminductor, affirm the functionality and adequacy of the proposed design. A Chua’s oscillator is realized using proposed VDDDA-based meminductor as non-linear element.

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