<?xml version="1.0" encoding="utf-8"?>
<journal>
<title>IRANIAN JOURNAL OF ELECTRICAL AND ELECTRONIC ENGINEERING</title>
<title_fa></title_fa>
<short_title>IJEEE</short_title>
<subject>Engineering &amp; Technology</subject>
<web_url>http://ijeee.iust.ac.ir</web_url>
<journal_hbi_system_id>18</journal_hbi_system_id>
<journal_hbi_system_user>agent2</journal_hbi_system_user>
<journal_id_issn>1735-2827</journal_id_issn>
<journal_id_issn_online>1735-2827</journal_id_issn_online>
<journal_id_pii></journal_id_pii>
<journal_id_doi></journal_id_doi>
<journal_id_iranmedex></journal_id_iranmedex>
<journal_id_magiran></journal_id_magiran>
<journal_id_sid></journal_id_sid>
<journal_id_nlai></journal_id_nlai>
<journal_id_science></journal_id_science>
<language>en</language>
<pubdate>
	<type>jalali</type>
	<year>1404</year>
	<month>12</month>
	<day>1</day>
</pubdate>
<pubdate>
	<type>gregorian</type>
	<year>2026</year>
	<month>3</month>
	<day>1</day>
</pubdate>
<volume>22</volume>
<number>2</number>
<publish_type>online</publish_type>
<publish_edition>1</publish_edition>
<article_type>fulltext</article_type>
<articleset>
	<article>


	<language>en</language>
	<article_id_doi></article_id_doi>
	<title_fa></title_fa>
	<title>Contemplation of QCA based Cryptographic Nano Communication Circuit using Multilayer Approach</title>
	<subject_fa>2-VLSI</subject_fa>
	<subject>VLSI</subject>
	<content_type_fa>Research Paper </content_type_fa>
	<content_type>Research Paper </content_type>
	<abstract_fa></abstract_fa>
	<abstract>&lt;span style=&quot;font-size:10.0pt&quot;&gt;&lt;span new=&quot;&quot; roman=&quot;&quot; style=&quot;font-family:&quot; times=&quot;&quot;&gt;CMOS technology, after contributing a lot to electronics world, is now facing difficulties in designing of more efficient circuits in terms of compactness, power efficiency and speed. It is happening due to various side effects being generated on account of further down scaling of feature size. The Quantum Dot Cellular Automata (QCA) technology seems to be alternate and promising technology for designing of more efficient circuits. The cryptographic encoder and decoder are the key component for secure and safe communication. This paper presents an efficient design of 1:2 demultiplexer, 1:4 demultiplexer and 4:1 multiplexer which are further used to design a cryptographic nano communication circuit. The proposed circuits are efficient in terms of energy, area and speed. The architectures are designed through multilayer approach in QCA technology that makes it compact. The efficiency of the proposed circuits has been verified through the tool QCA Designer 2.0.3.&lt;/span&gt;&lt;/span&gt;</abstract>
	<keyword_fa></keyword_fa>
	<keyword>Quantum Dot Cellular Automata, multiplexer, demultiplexer, multilayer design, cryptographic architecture, nano communication.</keyword>
	<start_page>136</start_page>
	<end_page>149</end_page>
	<web_url>http://ijeee.iust.ac.ir/browse.php?a_code=A-10-4705-1&amp;slc_lang=en&amp;sid=1</web_url>


<author_list>
	<author>
	<first_name>Paramjeet</first_name>
	<middle_name></middle_name>
	<last_name>.</last_name>
	<suffix></suffix>
	<first_name_fa></first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa></last_name_fa>
	<suffix_fa></suffix_fa>
	<email>chauhan.paramjeet@gmail.com</email>
	<code>1800319475328460017726</code>
	<orcid>1800319475328460017726</orcid>
	<coreauthor>No</coreauthor>
	<affiliation>Department of Electronics and Communication Engineering, Faculty of Engineering and Technology, SRM Institute of Science and Technology, Delhi-NCR Campus, Modinagar, Ghaziabad 201204, U.P., India.</affiliation>
	<affiliation_fa></affiliation_fa>
	 </author>


	<author>
	<first_name>Saptarshi</first_name>
	<middle_name></middle_name>
	<last_name>Gupta</last_name>
	<suffix></suffix>
	<first_name_fa></first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa></last_name_fa>
	<suffix_fa></suffix_fa>
	<email>ece.saptarshi@gmail.com</email>
	<code>1800319475328460017727</code>
	<orcid>1800319475328460017727</orcid>
	<coreauthor>Yes
</coreauthor>
	<affiliation>Department of Electronics and Communication Engineering, Faculty of Engineering and Technology, SRM Institute of Science and Technology, Delhi-NCR Campus, Modinagar, Ghaziabad 201204, U.P., India.</affiliation>
	<affiliation_fa></affiliation_fa>
	 </author>


	<author>
	<first_name>Rupali</first_name>
	<middle_name></middle_name>
	<last_name>Singh</last_name>
	<suffix></suffix>
	<first_name_fa></first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa></last_name_fa>
	<suffix_fa></suffix_fa>
	<email>rupal.rishi@gmail.com</email>
	<code>1800319475328460017728</code>
	<orcid>1800319475328460017728</orcid>
	<coreauthor>No</coreauthor>
	<affiliation>Department of Electronics and Communication Engineering, Faculty of Engineering and Technology, SRM Institute of Science and Technology, Delhi-NCR Campus, Modinagar, Ghaziabad 201204, U.P., India.</affiliation>
	<affiliation_fa></affiliation_fa>
	 </author>


</author_list>


	</article>
</articleset>
</journal>
