<?xml version="1.0" encoding="utf-8"?>
<journal>
<title>IRANIAN JOURNAL OF ELECTRICAL AND ELECTRONIC ENGINEERING</title>
<title_fa></title_fa>
<short_title>IJEEE</short_title>
<subject>Engineering &amp; Technology</subject>
<web_url>http://ijeee.iust.ac.ir</web_url>
<journal_hbi_system_id>18</journal_hbi_system_id>
<journal_hbi_system_user>agent2</journal_hbi_system_user>
<journal_id_issn>1735-2827</journal_id_issn>
<journal_id_issn_online>1735-2827</journal_id_issn_online>
<journal_id_pii></journal_id_pii>
<journal_id_doi></journal_id_doi>
<journal_id_iranmedex></journal_id_iranmedex>
<journal_id_magiran></journal_id_magiran>
<journal_id_sid></journal_id_sid>
<journal_id_nlai></journal_id_nlai>
<journal_id_science></journal_id_science>
<language>en</language>
<pubdate>
	<type>jalali</type>
	<year>1404</year>
	<month>12</month>
	<day>1</day>
</pubdate>
<pubdate>
	<type>gregorian</type>
	<year>2026</year>
	<month>3</month>
	<day>1</day>
</pubdate>
<volume>22</volume>
<number>2</number>
<publish_type>online</publish_type>
<publish_edition>1</publish_edition>
<article_type>fulltext</article_type>
<articleset>
	<article>


	<language>en</language>
	<article_id_doi></article_id_doi>
	<title_fa></title_fa>
	<title>Physics-Informed Neural Network-Assisted Compact Modeling of UTB-SOI and Nanowire MOSFETs for Ultra-Low Power Edge-AI Applications</title>
	<subject_fa>2-VLSI</subject_fa>
	<subject>VLSI</subject>
	<content_type_fa>Research Paper </content_type_fa>
	<content_type>Research Paper </content_type>
	<abstract_fa></abstract_fa>
	<abstract>&lt;span lang=&quot;EN-IN&quot; style=&quot;font-size:10.0pt&quot;&gt;&lt;span new=&quot;&quot; roman=&quot;&quot; style=&quot;font-family:&quot; times=&quot;&quot;&gt;Physics-informed neural networks (PINNs) offer a promising route to bridge device-level simulations and compact circuit models. In this work, we present a hybrid modeling framework that integrates TCAD datasets with a baseline compact model and applies a PINN correction to capture stress-condition effects with high fidelity. The proposed approach achieves &amp;le; 2% route mean square error (RMSE) across more than 2,000 bias points, maintaining stable predictions under temperature (273&amp;ndash;373 K) and radiation (0&amp;ndash;100 krad) variations. Extracted Berkeley Short-channel IGFET Model (BSIM) parameters enable direct SPICE simulation, ensuring compatibility with standard circuit design workflows. For deployment, the trained PINN is exported as a quantized ONNX model, achieving sub-millisecond inference and ultra-low energy consumption (0.25 pJ/op) on a Cortex-M55 platform. This dual pathway supports both high-accuracy circuit simulation and real-time edge inference, making it suitable for embedded applications under constrained conditions. Comparative analysis with recent ANN-based models confirms that our physics-informed approach offers superior interpretability, SPICE readiness, and deployment efficiency. All datasets, code, and models are released to support reproducibility, benchmarking, and further research in compact modeling and edge-AI integration.&lt;/span&gt;&lt;/span&gt;</abstract>
	<keyword_fa></keyword_fa>
	<keyword>Physics informed neural network, Compact model, SPICE, ONNX quantization, Edge-AI.</keyword>
	<start_page>119</start_page>
	<end_page>135</end_page>
	<web_url>http://ijeee.iust.ac.ir/browse.php?a_code=A-10-6009-1&amp;slc_lang=en&amp;sid=1</web_url>


<author_list>
	<author>
	<first_name>Balamanikandan</first_name>
	<middle_name></middle_name>
	<last_name>A</last_name>
	<suffix></suffix>
	<first_name_fa></first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa></last_name_fa>
	<suffix_fa></suffix_fa>
	<email>balamanikandan.a@mbu.asia</email>
	<code>1800319475328460017720</code>
	<orcid>1800319475328460017720</orcid>
	<coreauthor>Yes
</coreauthor>
	<affiliation>Department of Electronics and Communication Engineering, Mohan Babu University (Erstwhile SreeVidyanikethan Engineering College), Tirupati, India.</affiliation>
	<affiliation_fa></affiliation_fa>
	 </author>


	<author>
	<first_name>Venkataramanaiah</first_name>
	<middle_name></middle_name>
	<last_name>N</last_name>
	<suffix></suffix>
	<first_name_fa></first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa></last_name_fa>
	<suffix_fa></suffix_fa>
	<email>nvr.personal@gmail.com</email>
	<code>1800319475328460017721</code>
	<orcid>1800319475328460017721</orcid>
	<coreauthor>No</coreauthor>
	<affiliation>Department of Electronics and Communication engineering, Audisankara (Deemed to be university) (Erstwhile Audisankara College of Engineering &amp; Technology), Gudur, India.</affiliation>
	<affiliation_fa></affiliation_fa>
	 </author>


	<author>
	<first_name>Sukanya</first_name>
	<middle_name></middle_name>
	<last_name>M</last_name>
	<suffix></suffix>
	<first_name_fa></first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa></last_name_fa>
	<suffix_fa></suffix_fa>
	<email>sukanyavisagan@gmail.com</email>
	<code>1800319475328460017722</code>
	<orcid>1800319475328460017722</orcid>
	<coreauthor>No</coreauthor>
	<affiliation>Department of Electrical and Electronics Engineering, Adhiyamaan College of Engineering, Hosur, India.</affiliation>
	<affiliation_fa></affiliation_fa>
	 </author>


	<author>
	<first_name>Sudhakar Reddy</first_name>
	<middle_name></middle_name>
	<last_name>N</last_name>
	<suffix></suffix>
	<first_name_fa></first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa></last_name_fa>
	<suffix_fa></suffix_fa>
	<email>sudhakar1784@gmail.com</email>
	<code>1800319475328460017723</code>
	<orcid>1800319475328460017723</orcid>
	<coreauthor>No</coreauthor>
	<affiliation>Department of Electronics and Communication Engineering, Mohan Babu University (Erstwhile SreeVidyanikethan Engineering College), Tirupati, India.</affiliation>
	<affiliation_fa></affiliation_fa>
	 </author>


	<author>
	<first_name>Gomathy</first_name>
	<middle_name></middle_name>
	<last_name>G</last_name>
	<suffix></suffix>
	<first_name_fa></first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa></last_name_fa>
	<suffix_fa></suffix_fa>
	<email>gomathy.paul@gmail.com</email>
	<code>1800319475328460017724</code>
	<orcid>1800319475328460017724</orcid>
	<coreauthor>No</coreauthor>
	<affiliation>Department of Electrical and Electronics Engineering, Jaya Engineering college, Thiruninravur, India.</affiliation>
	<affiliation_fa></affiliation_fa>
	 </author>


	<author>
	<first_name>Venkatachalam</first_name>
	<middle_name></middle_name>
	<last_name>K</last_name>
	<suffix></suffix>
	<first_name_fa></first_name_fa>
	<middle_name_fa></middle_name_fa>
	<last_name_fa></last_name_fa>
	<suffix_fa></suffix_fa>
	<email>venkatmek12@gmail.com</email>
	<code>1800319475328460017725</code>
	<orcid>1800319475328460017725</orcid>
	<coreauthor>No</coreauthor>
	<affiliation>Department of Electronics and Communication engineering, Audisankara (Deemed to be university) (Erstwhile Audisankara College of Engineering &amp; Technology), Gudur, India.</affiliation>
	<affiliation_fa></affiliation_fa>
	 </author>


</author_list>


	</article>
</articleset>
</journal>
