Showing 26 results for Amp
Z. Nasiri-Gheidari, H. Lesani, F. Tootoonchian,
Volume 2, Issue 3 (7-2006)
Abstract
Hunting is a flutter associated with the synchronous speed that gives rise to the
gyro drifting errors and may cause objectionable time-displacement errors in video head
wheel drives and other precision scanning systems. In this paper, dynamic characteristics of
permanent Magnet hysteresis motors are presented and hunting is explained. New damping
techniques have been developed using optimized eigenvalues calculation. They are
calculated from LQR optimization method. In this damping method, a distinct reduction in
hunting has been archived. Furthermore field oriented control result of motor is presented
that have good effect on Hunting. Nearest agreement between simulated and measurement
results shows the accuracy of motor model. Comparison between this paper results and
other measured damping methods result are shown its success.
K. Malekian, J. Milimonfared, B. Majidi,
Volume 5, Issue 1 (3-2009)
Abstract
The main theme of this paper is to present novel controller, which is a genetic
based fuzzy Logic controller, for interior permanent magnet synchronous motor drives with
direct torque control. A radial basis function network has been used for online tuning of the
genetic based fuzzy logic controller. Initially different operating conditions are obtained
based on motor dynamics incorporating uncertainties. At each operating condition, a
genetic algorithm is used to optimize fuzzy logic parameters in closed-loop direct torque
control scheme. In other words, the genetic algorithm finds optimum input and output
scaling factors and optimum number of membership functions. This optimization procedure
is utilized to obtain the minimum speed deviation, minimum settling time, zero steady-state
error. The control scheme has been verified by simulation tests with a prototype interior
permanent magnet synchronous motor.
S. H Mirhosseini, A. Ayatollahi,
Volume 6, Issue 4 (12-2010)
Abstract
Abstract- A novel low-voltage two-stage operational amplifier employing resistive biasing is presented. This amplifier implements neutralization and correction common mode stability in second stage while employs capacitive dc level shifter and coupling between two stages. The structure reduces the power consumption and increases output voltage swing. The compensation is performed by simple miller method. For each stage an independent common-mode feedback circuits has been used. Simulation results show that power consumption is 2.1 mW at 1V supply. The dc gain of the amplifier is about 70 dB while its output swing is as high as around 1.2V.
J. Soleimani, A. Vahedi, S. M Mirimani,
Volume 7, Issue 4 (12-2011)
Abstract
Recently, Inner permanent magnet (IPM) synchronous machines have been
introduced as a possible traction motor in hybrid electric vehicle (HEV) and traction
applications due to their unique merits. In order to achieve maximum torque per ampere
(MTPA), optimization of the motor geometry parameters is necessary. This paper Presents
a design method to achieve minimum volume, MTPA and minimum value of cogging
torque for traction IPM synchronous machines and simulation in order to extract the output
values of motor is done using 3D-Finite Element Model, that has high level of accuracy and
gives us a better insight of motor performance. Then presents back EMF, power factor,
cogging torque, Flux density, torque per ampere diagram, CPSR (constant power speed
ratio), torque per speed diagram in this IPM synchronous machine. This study can help
designers in design approach of such motors.
E. Afjei,
Volume 8, Issue 2 (6-2012)
Abstract
The switched reluctance motor is a singly excited, doubly salient machine which
can be used in generation mode by selecting the proper firing angles of the phases. Due to
its robustness, it has the potential and the ability to become one the generators to be used in
harsh environment. This paper presents an energy conversion by a Switched Reluctance
Generator (SRG) when bifilar converter circuit and discrete position sensors are employed.
As the generator’s speed increases by a prime mover the shape of current waveform
changes in such a way that limits the production of generating voltage. At high speeds, it is
possible for the phase current never reaches the desired value to produce enough back-emf
for sufficient voltage generation, therefore, the output power falls off. In order to remedy
this problem, the phase turn on angle is advanced in a way that the phase commutation
begins sooner. Since one of the advantages of this type of generator is its variable speed
then, the amount of advancing for the turn on angle should be accomplished automatically
to obtain the desired output voltage according to the speed of the generator, meaning, as the
generator speed increases so should the turn on angle and vice versa. In this respect, this
paper introduces an electronic circuit in conjunction with the position sensors and the drive
converter to achieve this task for a desired output voltage when a SRG feeding a resistive
load. To evaluate the generator performance, two types of analysis, namely numerical
technique and experimental studies have been utilized on a 6 by 4, 30 V, SRG. In the
numerical analysis, due to highly non-linear nature of the motor, a three dimensional finite
element analysis is employed, whereas in the experimental study, a proto-type generator
and its circuitries have been built and tested using bifilar converter. A linear analysis of the
current waveform for the generator under different advancements of the turn on angle has
been performed numerically and experimentally and the results are presented.
R. Mirzalou, A. Nabavi, Gh. Darvish,
Volume 8, Issue 3 (9-2012)
Abstract
This paper presents a new ultra-wideband LNA which employs the complementary derivative superposition method in noise cancellation structure. A pMOS transistor in weak inversion region is employed for simultaneous second- and third-order distortion cancellation. Source-degeneration technique and two shunt inductors are added to improve the performance at high frequencies. The degeneration inductor resonates at fT/2 and realizes a new input matching technique that widens the bandwidth with decreasing its quality factor and input capacitance, while flattens the input resistance and also improves the 1dB Compression Point. The shunt inductors resonate at the center frequency of the band and improve the effective bandwidth of noise/distortion cancellation technique. This LNA has been designed in a 0.18-μm CMOS process and consumes 8.3 mA from 1.8 V power supply. The chip area is 0.55mm2. The noise figure and voltage gain are 4.48-5.18 dB and 13 dB, respectively. S11 is lower than -13.5 dB over 5.8–10.6 GHz and IIP3 is 14.5–17.5 dBm, IIP2 is 14–15.5 dBm. This technique improves IIP3 more than 9dB.
S. Ghavami, B. Abolhassani,
Volume 9, Issue 1 (3-2013)
Abstract
In the down link scenario of code division multiple access (CDMA) systems, multi user detectors (MUDs) such as linear de-correlating detector (LDDs) provide satisfactory symbol error rates (SERs) at the expense of much increased complexity, they require all active users’ spreading sequences, which is impractical from privacy point of view. To overcome this impracticality, a simple matched filter receiver is considered in this paper, which requires no knowledge of co-users’ spreading sequences. However, this simple receiver degrades the SER due to multiple access interference (MAI). To overcome this SER degradation, a zero force (ZF) pre-coder is employed in the transmitter traditionally. Moreover, a composite of CDMA signals has a large peak to average power ratio (PAPR), which causes nonlinear distortion (NLD) at the output of the base station high power amplifier (HPA). This also results in degrading the SER. We analyze the down link scenario of CDMA system to derive an equation for the SER of system with ZF-pre-coder plus HPA in the transmitter and matched filter in the receiver over two cases: additive white Gaussian noise (AWGN) and AWGN plus flat fading channels. Theoretical analysis and numerical results show that the ZF pre-coder increases the total degradation of the link significantly compared with that of the LDD. So, as a solution, rather than using ZF pre-coder, we propose a new method which is called extended joint channel estimation method, it is based on joint estimation of channel gains and LDD operator by the mobile station (MS). In that base station (BS) transmits the row k of LDD operator to the MS k. Simulation results show that the SER of this new proposed method is matched to that of LDD in AWGN channel when the number of pilot symbol repetition is equal to 8. Moreover, this method has the two added advantages of no need for providing the spreading sequences of all co-users and meeting a satisfactory total degradation. Furthermore, our analysis shows that loss in spectral efficiency due to transmitting the pilot symbols in the proposed method is negligible for the practical values of traffic variations.
A Ghorbani-Nejad, A Jannesari,
Volume 9, Issue 4 (12-2013)
Abstract
A two stage sub-µW Inverter-based switched-capacitor amplifier-filter is presented which is capable of amplifying both spikes and local field potentials (LFP) signals. Here we employ a switched capacitor technique for frequency tuning and reducing of 1/f noise of two stages. The reduction of power consumption is very necessary for neural recording devices however, in switched capacitor (SC) circuits OTA is a major building block that consumes most of the power. Therefore an OTA-less technique utilizing a class-C inverter is employed that significantly reduces the power consumption. A detailed analysis of noise performance for the inverter-based SC circuits is presented. A mathematical model useful for analysis of such SC integrators is derived and a good comparison is obtained between simulation and analytical technique. With a supply voltage of 0.7V and using 0.18 µm CMOS technology, this design can achieves a power consumption of about 538 nW. The designed amplifier-filter has the gains 18.6 dB and 28.2 dB for low pass only and cascaded filter, respectively. By applying different sampling frequencies, the filter attains a reconfigurable bandwidth.
K. Mokhtari, M. Mirzaie, M. Shahabi,
Volume 11, Issue 1 (3-2015)
Abstract
This paper aims to measure and analyze of the leakage current of 20 kV polymer and porcelain metal oxide surge arresters under humid ambient conditions by applying different voltages to the arresters terminal. The characteristics of the leakage currents at that stage have been investigated when changes in the ambient humidity were introduced in an artificial fog chamber. It is assumed that magnitude of the noise level during the tests is constant. The frequency and resistive component peak efficient analysis can then be done on the leakage current signal. The idea behind this is to get indicators for investigating of surge arrester behavior in humid conditions. Two important indicators were obtained to evaluate the behavior of the surge arrester in humid conditions
M. Mohammadian, H. R. Momeni, M. Tahmasebi,
Volume 11, Issue 3 (9-2015)
Abstract
Artificially regulating gene expression is an important step in developing new
treatment for system-level disease such as cancer. In this paper, we propose a method to
regulate gene expression based on sampled-data measurements of gene products
concentrations. Inherent noisy behaviour of Gene regulatory networks are modeled with
stochastic nonlinear differential equation. To synthesize feedback controller, we formulate
sampling process as an impulsive system. By using a new Lyapunov function with
discontinuities at sampling times, state feedback gain that guarantees exponential meansquare
stability and H&infin performance is derived from LMIs. These LMIs also determine the
maximum allowable time between sampling points. A numerical example and a practical
application are presented to justify the applicability of the theoretical results
S. Sivasakthi, R. K. Santhi, N. Murali Krishnan, S. Ganesan, S. Subramanian,
Volume 13, Issue 2 (6-2017)
Abstract
The increasing concern of global climate changes, the promotion of renewable energy sources, primarily wind generation, is a welcome move to reduce the pollutant emissions from conventional power plants. Integration of wind power generation with the existing power network is an emerging research field. This paper presents a meta-heuristic algorithm based approach to determine the feasible dispatch solution for wind integrated thermal power system. The Unit Commitment (UC) process aims to identify the best feasible generation scheme of the committed units such that the overall generation cost is reduced, when subjected to a variety of constraints at each time interval. As the UC formulation involves many variables and system and operational constraints, identifying the best solution is still a research task. Nowadays, it is inevitable to include power system reliability issues in operation strategy. The generator failure and malfunction are the prime influencing factor for reliability issues hence they have considered in UC formulation of wind integrated thermal power system. The modern evolutionary algorithm known as Grey Wolf Optimization (GWO) algorithm is applied to solve the intended UC problem. The potential of the GWO algorithm is validated by the standard test systems. Besides, the ramp rate limits are also incorporated in the UC formulation. The simulation results reveal that the GWO algorithm has the capability of obtaining economical resolutions with good solution quality.
E. Babaei, T. Ahmadzadeh,
Volume 13, Issue 4 (12-2017)
Abstract
First of all, in this paper, the topology and operation of the three-phase three-level Z-source inverter based on neutral-point-clamped (Z-NPC) are studied. Moreover, different combinations of permissible switching states and control signals are explained for this inverter. In this paper, the topology of the three-phase three-level Z-NPC inverter is extended for an n-level state. Also, a combination of allowed switching states with relevant mathematical equations is presented for the proposed n-level Z-NPC inverter. In comparison with multilevel voltage-source inverters (only voltage-boost capability), the proposed multilevel Z-NPC inverter is a single-stage converter and it has a buck-boost capability of voltage. On the other hand, the control of two-stage converters compared to single-stage converters can be more difficult because of existing more active and passive components. In this paper, two new PWM control methods are also proposed for various multilevel Z-NPC inverters. One advantage of the proposed PWM control methods in comparison with conventional PWM control methods is maintaining the charge balance of the dc-link capacitors in neutral point. The correct performance of the proposed multilevel Z-NPC topology and PWM control methods are verified by the obtained results of analysis and simulations performed in the PSCAD software.
S. R. Sadu, P. V. Prasad, G. N. Srinivas,
Volume 14, Issue 1 (3-2018)
Abstract
This paper presents the comparative study of three phase twenty five level diode clamped and cascaded H-bridge multilevel inverters. The comparison is made in respect of requirement of devices, quality of output voltage and reduction of total harmonic distortion at the multilevel inverter terminals. In this work multicarrier sinusoidal pulse modulation control methods of Phase disposition (PD-PWM), phase opposition disposition (POD-PWM) and Alternative Phase Opposition Disposition (APOD-PWM) pulse width modulation control strategies are applied for both diode clamped and cascaded H-bridge multilevel inverters and compared its total harmonic distortion. The performance of both diode and cascaded H-bridge multilevel inverters is investigated and compared. Based on simulation results it is observed that the output voltage of the cascaded H-bridge multilevel inverters is better as compared to the diode clamped multilevel inverter. The proposed multilevel inverters are simulated using MATLAB/Simulink software.
H. Faraji Baghtash, Kh. Monfaredi,
Volume 15, Issue 3 (9-2019)
Abstract
A novel active feedback frequency compensation scheme is presented in this work. Based on the proposed technique, an amplifier with two main poles in its frequency bandwidth can be easily compensated by introducing a pole-zero pair in a local feedback. The proposed method is mathematically analyzed and then based on the derived formulations, a design procedure is established. The capability of the proposed technique is examined considering a well-known two-stage amplifier, considering just a trivial modification on its input stage. To gain an analogous and fair insight, the performance of the proposed structure is compared with that is of the optimally designed miller-compensated two-stage amplifier. The post-layout simulations are accomplished with TSMC 180nm CMOS standard technology. The Spectre post-layout simulations show that the proposed structure outperforms the traditional structure in terms of power consumption and gain bandwidth product. The robustness of the design is checked with Monte Carlo simulations.
S. Juneja, R. Sharma,
Volume 15, Issue 4 (12-2019)
Abstract
Design of Global Positioning System (GPS) receiver with a low noise amplifier (LNA) in the front end remains a major design requirement for the success of modern day navigation and communication system. Any LNA is expected to meet the requirements like its ability to add the least amount of noise while providing sufficient gain, perfect input and output matching, and high linearity. However, most of the reported designs of LNAs present the need for striking a trade-off between these design parameters in order to obtain the desired performance for a particular RF receiver. This paper presents high gain (21dB), high input matched (-29dB), high reverse isolation (-41dB) and low noise figure (< 2dB) narrowband LNA for extremely low power level GPS L1 band signals broadcasting at 1.57GHz with a channel bandwidth of 10MHz. Inductive source degeneration topology is employed for the design and all the matching inductors in the circuit are used with fixed quality factor (Q) to model the losses for better tuning and matching. The design is carried out on Cadence Virtuoso Tool version IC6.1.6 and Spectre version MMSIM13.1 at 0.18µm technology node using a generic process development kit. Detailed mathematical analysis of the design is done and all the DC parameters like values of transconductance, gate source capacitance, drain source voltage, drain current, etc. are reported. Graphical analysis using Smith chart is carried out to present the results and to bring forth the trade-offs involved in the design. LNA draws 5mA current from 1.2V supply voltage and offers good linearity that is sufficient for GPS application and is measured by input intercept point 3 (IIP3 < ‑4dBm).
M. Khalaj-Amirhosseini, M. Nadi-Abiz,
Volume 16, Issue 2 (6-2020)
Abstract
Phase Perturbation Method (PPM) is introduced as a new phase-only synthesis method to design reflectarray antennas so as their sidelobe level is reduced. In this method, only the reflected phase of conventional unit cells are perturbed from their required values. To this end, two approaches namely the conventional Optimization method and newly introduced Phase to Amplitude Approximation (PAA) method are proposed. Finally, a reflectarray antenna is designed and fabricated to have a low sidelobe level and its performance is investigated.
M. Khalaj-Amirhosseini,
Volume 17, Issue 2 (6-2021)
Abstract
Nonuniform Phased Sampling method is proposed to phase-only synthesize the power pattern of both linear and planar antenna arrays. This method modifies the conventional sampling method which is used for amplitude-phase synthesis. This method is based on assigning suitable phases to the sampling points of radiation pattern in order to reach desired amplitude of currents. Some examples are given to verify the effectiveness of the proposed method for both pencil-beam and shaped beam patterns.
H. Shayeghi, Y. Hashemi,
Volume 17, Issue 3 (9-2021)
Abstract
The main idea of this paper is proposing a model to develop generation units considering power system stability enhancement. The proposed model consists of two parts. In the first part, the indexes of generation expansion planning are ensured. Also, small-signal stability indexes are processed in the second part of the model. Stability necessities of power network are supplied by applying a set of robustness and performance criteria of damping. Two parts of the model are formulated as two-objective function optimization that is solved by adaptive non-dominated sorting genetic method-III (ANSGM-III). For better decision-making of the final solution of generation units, a set of Pareto-points have been extracted by ANSGM-III. To select an optimal solution among Pareto-set, an analytical hierarchy style is employed. Two objective functions are compared and suitable weights are allocated. Numerical studies are carried out on two test systems, 68-bus and 118-bus power network. The values of generation expansion planning cost and system stability index have been studied in different cases and three different scenarios. Studies show that, for example, in the 68-bus system for the case of system load growth of 5%, the cost of generation expansion planning for the proposed model increased by 7.7% compared to the previous method due to stability modes consideration and the small-signal stability index has been improved by 6.7%. The proposed model is survived with the presence of a wide-area stabilizer (WAS) for damping of oscillations. The effect of WAS latency on expansion programs is evaluated with different amounts of delay times.
G. Vasudeva, B. V. Uma,
Volume 18, Issue 3 (9-2022)
Abstract
Successive approximation register (SAR) analog to digital converter (ADC) architecture comprises submodules such as comparator, digital to analog converters (DAC), and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements, and ADC metrics are presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two-stage segmented resistive string DAC architecture, and low power SAR logic are designed and integrated to form the ADC architecture with a maximum sampling rate of 1 GS/s. Circuit schematic is captured in cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC are evaluated in MATLAB environment. Differential nonlinearity and integral nonlinearity metrics for the 12-bit ADC are limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency up to 1 GSps is designed in this work with low power dissipation of less than 10 mW.
M. Soruri, S. M. Razavi, M. Forouzanfar,
Volume 18, Issue 3 (9-2022)
Abstract
Power amplifier is one of the main components in the RF transmitters. It must provide various stringent features that can lead to complicating the design. In this paper, a new optimizing method based on the inclined planes system optimization algorithm is presented for the design of a discrete power amplifier. It is evaluated in a 2.4-3 GHz power amplifier, which is designed based on “Cree’s CGH40010F GaN HEMT”. The optimization goals are input and output return losses, Power Added Efficiency, and Gain. Large signal simulation of the optimized power amplifier shows a good performance across the bandwidth. In this frequency range, the input and output return losses are about lower than -10 dB, the Power Added Efficiency is greater than 51%, while the Gain is higher than 13.5 dB. A two-tone test with a frequency space of 1 MHz is applied for the linearity evaluation of the designed power amplifier. The obtained result shows that the power amplifier has good linearity with a low memory effect.
