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Showing 6 results for Multiplier

C. S. Vinitha, R. K. Sharma,
Volume 15, Issue 4 (12-2019)
Abstract

An efficient Lookup Table (LUT) design for memory-based multiplier is proposed.  This multiplier can be preferred in DSP computation where one of the inputs, which is filter coefficient to the multiplier, is fixed. In this design, all possible product terms of input multiplicand with the fixed coefficient are stored directly in memory. In contrast to an earlier proposition Odd Multiple Storage (OMS), we have proposed utilizing Even Multiple Storage (EMS) scheme for memory-based multiplication and by doing so we are able to achieve a less complex and high-speed design. Because of the very simpler control circuit used in our design, to extract the odd multiples of the product term, we are also able to achieve a significant reduction in path delay and area complexity. For validation, the proposed design of the multiplier is coded in VHDL, simulated and synthesized using Xilinx tool and then implemented in Virtex 7 XC7vx330tffg1157 FPGA. Various key performance metrics like number of slices, number of slice LUT’s and maximum combinational path delay is estimated for different input word length. Also, the performance metrics are compared with the existing OMS design. It is found that the proposed EMS design occupies nearly 62% less area in terms of number of slices as compared to the OMS design and the maximum path delay is decreased by 77% for a 64-bit input. Further, the proposed multipliers are used in Transposed FIR filter and its performance is compared with the OMS multiplier based filter for various filter orders and various input lengths.

S. Pourjafar, H. Shayeghi, H. Madadi Kojabadi, M. Maalandish, F. Sedaghati,
Volume 16, Issue 1 (3-2020)
Abstract

In this work, a non-isolated high step up DC-DC converter using coupled inductor and voltage multiplier cell is proposed. The proposed converter conversion ratio is efficiently extended by using a coupled inductor. An interleaved configuration of two diode-capacitor cells is applied to step up the voltage conversion ratio and decrease the voltage stress across the switches. Also, in the suggested converter high voltage gain is provided by low turn ratio of the coupled inductor which decreases the volume of cores. Moreover, the reverse recovery problem of output diode is diminished by recycling the leakage inductance energy of the coupled inductor. It causes to increase the overall system efficiency. Furthermore, the voltage multiplier cells lead to clamp the voltage spikes through the switch, when the switch turns off. The comparison between the suggested converter and similar converters is provided to verify its advantages. To validate the effectiveness of the suggested converter, a 200W laboratory prototype with 20V input and 150V output voltages operating at 25kHz switching frequency is carried out and experimental test consequences are given.

R. Pinto,
Volume 16, Issue 4 (12-2020)
Abstract

Multiplication is a basic operation in any signal processing application. Multiplication is the most important one among the four arithmetic operations like addition, subtraction, and division. Multipliers are usually hardware intensive, and the main parameters of concern are high speed, low cost, and less VLSI area. The propagation time and power consumption in the multiplier are always high. The multiplier speed usually determines the speed of the processor. Hence in this work, a design of a 32-bit multiplier is proposed by modifying the conventional shift-add multiplier. The proposed structure reduces the power consumed by the technique of minimizing the switching activities in the design. A 32-bit parallel prefix adder based on the modified Ling equation is also proposed to speed up the addition of the partial products in the multiplier. The design is modeled in VHDL and implementation is carried out in CADENCE software with 90 nm and 180 nm CMOS technology.

A. Pathan, T. Memon,
Volume 17, Issue 4 (12-2021)
Abstract

FPGA’s block memory may be programmed as a single or dual-port RAM/ROM module that leads to an area-efficient implementation of memory-based systems. In this contest, various works of carrying out an optimized implementation of simple to complex DSP systems on embedded building blocks may be seen. The multiplier is a core element of the DSP systems, and in implementing a memory-based multiplier, it is observed that one of the operands is kept constant, hence leading the design to a constant-coefficient multiplication. This paper shows Virtex-7 FPGA’s dual-port ROM-based implementation of an 8x8 variable-coefficient multiplier that may be used in several simple to complex DSP applications. The novelty of the proposed design is to configure the block ROM in dual-port mode and, hence, get four partial products in two clock cycles and introduce two unconventional adder approaches for partial product addition. This approach leads to fully resource utilization and the provision of a variable-coefficient multiplier. The work also shows the comparison of proposed architecture with already existing memory-based implementations and concludes the work as a novel step towards the efficient memory-based implementation of multiplier core.

T. Mendez, S. G. Nayak,
Volume 18, Issue 1 (3-2022)
Abstract

The need for low-power VLSI chips is ignited by the enhanced market requirement for battery-powered end-user electronics, high-performance computing systems, and environmental concerns. The continuous advancement of the computational units found in applications such as digital signal processing, image processing, and high-performance CPUs has led to an indispensable demand for power-efficient, high-speed and compact multipliers. To address those low-power computational aspects with improved performance, an approach to design the multiplier using the algorithms of Vedic math is developed in this research. In the proposed work, the pre-computation technique is incorporated that aided in estimation of the carries during the partial product calculation stage; that enhanced the speed of the multiplier. This design was carried out using Cadence NCSIM 90 nm technology. The comparative analysis between the proposed multiplier design and the multipliers from the literature resulted in a substantial improvement in power dissipation as well as delay. The research was extended to assess the designed architectures’ performance statistically, applying the independent sample t-test hypothesis.

Amir Gallaj, Jaber Fallah Ardashir, Mojtaba Beiraghi,
Volume 18, Issue 4 (12-2022)
Abstract

This work proposes a high step-up interleaved dc/dc topology utilizing a VM (voltage multiplier) cell suitable for PV applications. The VM cells D/C (Diode/Cap.) are cascaded among the phases to approach a high voltage gain. Besides, the voltage converting ratio of the presented structure can be improved by extending the VM cells and it also leads to drop in the normalized voltage stress throughout the switches and some diodes. Therefore, by utilizing a semiconductor (Switch/Diode) with a lower rating leads to a decline in system losses. Also, the efficiency of the suggested topology will be considerable and the overall cost can be decreased. To elaborate on the main benefits of the proposed topology, a comparison has been made across other literature regarding the efficiency, peak voltage throughout the semiconductors and voltage ratio of the converter. To prove the accuracy principle of operation of the suggested converter, two prototypes (for n=1, 2 stages) were built and tested at 350 W and 453 W with an operating frequency of about 40 kHz performed.
 


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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.