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Showing 2 results for Markov Random Field (mrf)
A Design Methodology for Reliable MRF-Based Logic Gates
S. M. Razavi, S. M. Razavi,
Volume 15, Issue 3 (9-2019)
Abstract
Probabilistic-based methods have been used for designing noise tolerant circuits recently. In these methods, however, there is not any reliability mechanism that is essential for nanometer digital VLSI circuits. In this paper, we propose a novel method for designing reliable probabilistic-based logic gates. The advantage of the proposed method in comparison with previous probabilistic-based methods is its ultra-high reliability. The proposed method benefits from Markov random field (MRF) as a probabilistic framework and triple modular redundancy (TMR) as a reliability mechanism. A NAND gate is used to show the design methodology. The simulation results verify the noise immunity of the proposed MRF-based gate in the presence of noise. In addition, the values from reliability estimation program show the reliability of 0.99999999 and 0.99941316 for transistor failure rates of 0.0001 and 0.001, respectively, which are much better as compared with previous reported MRF-based designs.

A Minimal-Cost Inherent-Feedback Approach for Low-Power MRF-Based Logic Gates
S. M. Razavi, S. M. Razavi,
Volume 16, Issue 4 (12-2020)
Abstract
The Markov random field (MRF) theory has been accepted as a highly effective framework for designing noise-tolerant nanometer digital VLSI circuits. In MRF-based design, proper feedback lines are used to control noise and keep the circuits in their valid states. However, this methodology has encountered two major problems that have limited the application of highly noise immune MRF-based circuits. First, excessive hardware overhead that imposes a great cost, power consumption and propagation delay on the circuits and second, separate implementation of feedback lines that adds further delay to the circuits. In this paper, we propose a novel approach for minimal-cost inherent-feedback implementation of low-power MRF-based logic gates. The simulation results, which are based on 32nm BSIM4 models, demonstrate that besides excellent noise immunity of the proposed method, it has the least propagation delay in comparison with all of the previously reported MRF-based gates due to its inherent feedbacks. In addition, the proposed method outperforms competing ones, which have comparable noise immunity, in other circuit metrics like cost and power consumption. Specifically, the proposed method achieves at least 18%, 29%, and 39% reductions in cost, delay and power consumption with considerable noise immunity improvement compared with competing methods.

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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.