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Showing 4 results for Low Voltage
A Novel Very High Performance CMOS Current Mirror with extremely low input and ultra high output resistance
H. Faraji Baghtash, S. J. Azhari, Kh. Monfaredi,
Volume 7, Issue 4 (12-2011)
Abstract
In this paper a novel very high performance current mirror is presented. It favorably benefits from such excellent parameters as: Ultra high output resistance (36.9GΩ), extremely low input resistance (0.0058Ω), low output (~0.18V) and low input voltage (~0.18V) operation, very low power consumption (20μW), very low offset current (1pA), ultra wide current dynamic range (150dB), and ultra high accuracy (error = 0.003%). The circuit has a very simple compact architecture and uses a single 1V power supply. The qualitative performance of the circuit is validated with HSPICE simulations using HSPICE TSMC 0.18μm CMOS technology.
An Ultra High CMRR Low Voltage Low Power Fully Differential Current Operational Amplifier (COA)
A. Roohavar, S. J. Azhari,
Volume 11, Issue 4 (12-2015)
Abstract

this paper presents a novel fully differential (FD) ultra high common mode rejection ratio (CMRR) current operational amplifier (COA) with very low input impedance. Its FD structure that attenuates common mode signals over all stages grants ultra high CMRR and power supply rejection ratio (PSRR) that makes it suitable for mixed mode and accurate applications. Its performance is verified by HSPICE simulations using TSMC 0.18µm CMOS technology and ±0.75V supply voltage that indicate such outstanding results of 81.1dB gain,298MHz gain-bandwidth product, 64º phase margin, 28.2m&Omega input impedance, 159dB CMRR and PSRR+/PSRR- of 174dB/163dB all at low power consumption of 0.302mW.To study the robustness of the COA against technology and get such results close to measurement, Monte Carlo analysis is applied on both pre- layout and post layout simulations of the design. The results are as 73.29dB and 2.07MHz, 1.92&Omega, and150.35dB for Ai magnitude and bandwidth, Ri, and CMRR, respectively, in pre-layout case while change to 66.58dB and 1.44 MHz, 11.07 &Omega, and 147.10dB, for the same arrange, in post layout case. These measurement-like results thus, prove excellent practical performance of the proposed COA.

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A Novel Active Feedback Frequency Compensation Scheme for Two-Stage OTA
H. Faraji Baghtash, Kh. Monfaredi,
Volume 15, Issue 3 (9-2019)
Abstract
A novel active feedback frequency compensation scheme is presented in this work. Based on the proposed technique, an amplifier with two main poles in its frequency bandwidth can be easily compensated by introducing a pole-zero pair in a local feedback. The proposed method is mathematically analyzed and then based on the derived formulations, a design procedure is established. The capability of the proposed technique is examined considering a well-known two-stage amplifier, considering just a trivial modification on its input stage. To gain an analogous and fair insight, the performance of the proposed structure is compared with that is of the optimally designed miller-compensated two-stage amplifier. The post-layout simulations are accomplished with TSMC 180nm CMOS standard technology. The Spectre post-layout simulations show that the proposed structure outperforms the traditional structure in terms of power consumption and gain bandwidth product. The robustness of the design is checked with Monte Carlo simulations.

High Step-Up Interleaved DC/DC Converter Using VM Cell for PV Applications
Amir Gallaj, Jaber Fallah Ardashir, Mojtaba Beiraghi,
Volume 18, Issue 4 (12-2022)
Abstract
This work proposes a high step-up interleaved dc/dc topology utilizing a VM (voltage multiplier) cell suitable for PV applications. The VM cells D/C (Diode/Cap.) are cascaded among the phases to approach a high voltage gain. Besides, the voltage converting ratio of the presented structure can be improved by extending the VM cells and it also leads to drop in the normalized voltage stress throughout the switches and some diodes. Therefore, by utilizing a semiconductor (Switch/Diode) with a lower rating leads to a decline in system losses. Also, the efficiency of the suggested topology will be considerable and the overall cost can be decreased. To elaborate on the main benefits of the proposed topology, a comparison has been made across other literature regarding the efficiency, peak voltage throughout the semiconductors and voltage ratio of the converter. To prove the accuracy principle of operation of the suggested converter, two prototypes (for n=1, 2 stages) were built and tested at 350 W and 453 W with an operating frequency of about 40 kHz performed.
 

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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.