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Showing 3 results for Nayak

D. Kishan, P. S. R. Nayak, B. Naresh Kumar Reddy,
Volume 16, Issue 1 (March 2020)

In recent years, the popularity of wireless inductive power transfer (WIPT) system for electric vehicle battery charging (EVBC) is always ever-increasing. In the WIPT inductively coupled coil structure is the heart of the system and the mutual inductance (MI) between the coupled coils is the key factor for effective power transfer. This paper presents the analysis of mutual inductance between the spiral square coils based on the cross-sectional area ratio of spiral circular and spiral square coupled coils. The analytical computed MI values are compared with FEM (Ansys Maxwell) simulation and Experimental computed values. Finally, the designed spiral square coils are implemented in a laboratory prototype model and at the receiver side for effective electric vehicle (EV) battery charging a closed-loop PID controller is implemented for DC-DC buck converter. The effectiveness of the proposed controller has been tested by providing sudden changes in mutual coupling and change in reference value. The proposed system is suitable for both stationary and dynamic wireless EVBC.

T. Mendez, S. G. Nayak,
Volume 18, Issue 1 (March 2022)

The need for low-power VLSI chips is ignited by the enhanced market requirement for battery-powered end-user electronics, high-performance computing systems, and environmental concerns. The continuous advancement of the computational units found in applications such as digital signal processing, image processing, and high-performance CPUs has led to an indispensable demand for power-efficient, high-speed and compact multipliers. To address those low-power computational aspects with improved performance, an approach to design the multiplier using the algorithms of Vedic math is developed in this research. In the proposed work, the pre-computation technique is incorporated that aided in estimation of the carries during the partial product calculation stage; that enhanced the speed of the multiplier. This design was carried out using Cadence NCSIM 90 nm technology. The comparative analysis between the proposed multiplier design and the multipliers from the literature resulted in a substantial improvement in power dissipation as well as delay. The research was extended to assess the designed architectures’ performance statistically, applying the independent sample t-test hypothesis.

R. Samanth, S. G. Nayak, P. B. Nempu,
Volume 19, Issue 1 (March 2023)

In the CMOS circuit power dissipation is a major concern for VLSI functional units. With shrinking feature size, increased frequency and power dissipation on the data bus have become the most important factor compared to other parts of the functional units. One of the most important functional units in any processor is the Multiply-Accumulator unit (MAC). The current work focuses on the development of MAC unit bus encoders as well as the identification of an improved architecture for image processing applications. To reduce the power consumption in these functional units, two bus encoding architectures were developed by encoding data before it was sent on the data buses. One is MSB reference encoding, and another is Fourth and Fifth bit ANDing (FFA) without the need for an extra bus line with fewer transitions by using gray codes. The comparison of the proposed encoding architectures with the existing encoding architectures from the literature revealed an 8% to 36% significant improvement in power dissipation. The simulation was done with Xilinx ISE, and the Cadence RTL Compiler tool was utilized for the synthesis, which was done with the 180nm technology library. And also, the image filtering is analyzed using MATLAB.

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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.