Showing 9 results for Kumar
A. Kumar, B. Chaturvedi,
Volume 14, Issue 2 (June 2018)
Abstract
This paper introduces four new resistorless circuits of first-order current-mode all-pass filter (CMAPF) based on dual-X current conveyor transconductance amplifier (DXCCTA). All the four circuits use a single DXCCTA and a capacitor for their realization. The main features of the proposed CMAPFs are: use of minimum active and passive components, resistorless realization, electronically adjustable pole frequency, easily cascadable, good sensitivity performance with respect to active and passive elements, low total harmonic distortion of output current (0.74%) and good operating frequency range (39.2 MHz). The non-ideal analysis of the proposed circuits has also been explored. Moreover, two applications of the proposed first-order CMAPF in terms of second order CMAPF and current-mode quadrature oscillator are also presented. HSPICE simulations have been carried out with 0.18 µm CMOS process parameters to validate the proposed circuits.
A. Kumar, P. Kumar,
Volume 15, Issue 4 (December 2019)
Abstract
This paper presents the three topologies of three-phase four-wire DSTATCOM for reduction of harmonics, reactive power compensation, increasing power factor, which occur due to a nonlinear load, environment problem and polluted grid. The performances of the above topologies have been compared for the magnitude of source current, power factor improvement, DC-link voltage regulation, and total harmonic distortion. This paper presents a novel work for the new young scientist /industrialist who working in the improvement of power quality in the grid. This paper helps to provide the application, designing constraints of shunt active filter in many fields. The First topology which is used in this paper is the three-phase four-wire four-pole voltage source converter based DSTATCOM. The second is the three-phase four-wire with three-leg voltage source converter based DSTATCOM with T-connected transformer and the third topology is the three H-bridge voltage source converter based DSTATCOM. The T-connected transformer in the second topology has been used to reduce the rating for voltage source converter. Synchronous reference frame theory based controller has been proposed to the generation of the reference current. Reference current generated from the synchronous frame theory is processed to hysteresis current controller loop which produces switching pulses for VSC based DSTATCOM. All these topologies have been implemented in MATLAB /Simulink platform by using different types of loading conditions such as resistive and power electronics load.
D. Kishan, P. S. R. Nayak, B. Naresh Kumar Reddy,
Volume 16, Issue 1 (March 2020)
Abstract
In recent years, the popularity of wireless inductive power transfer (WIPT) system for electric vehicle battery charging (EVBC) is always ever-increasing. In the WIPT inductively coupled coil structure is the heart of the system and the mutual inductance (MI) between the coupled coils is the key factor for effective power transfer. This paper presents the analysis of mutual inductance between the spiral square coils based on the cross-sectional area ratio of spiral circular and spiral square coupled coils. The analytical computed MI values are compared with FEM (Ansys Maxwell) simulation and Experimental computed values. Finally, the designed spiral square coils are implemented in a laboratory prototype model and at the receiver side for effective electric vehicle (EV) battery charging a closed-loop PID controller is implemented for DC-DC buck converter. The effectiveness of the proposed controller has been tested by providing sudden changes in mutual coupling and change in reference value. The proposed system is suitable for both stationary and dynamic wireless EVBC.
Pravat Biswal, Veera Venkata Subrahmanya Kumar Bhajana, Pavel Drabek,
Volume 18, Issue 4 (December 2022)
Abstract
This paper proposes two new soft-switching transformerless converters with high voltage conversion ratio. These proposed converters achieve soft-switching each with a single auxiliary resonant cell. The merit of these converters is reduced switching losses with lesser number of devices. The main switching devices are turned off with zero current switching (ZCS). Apart from the soft-switching feature, the voltage conversion ratio is increased in comparison with the existing topologies. The operating principles and the simulation results on 12V/200V/500W converter system are presented in this paper.
Mitesh Kumar, Shivam Shivam,
Volume 18, Issue 4 (December 2022)
Abstract
The idea of a microgrid is created by utilizing more diverse ac or dc distributed generation (DG) sources along with an energy storage system (ESS) and loads. The most efficient and reliable selection of ac and dc microgrids is a hybrid ac/dc microgrid. The hybrid microgrid largely overcomes the shortcomings of standalone ac or dc microgrids. A bidirectional interlinking converter (BIC) is utilized in the interface for controlling power flow between subgrids. In order to improve voltage and frequency regulation with effective power sharing, the BIC based on the proposed control scheme is implemented for power flow between ac and dc sub-grid in Islanding mode. The control scheme is modified based on conventional droop control with voltage and frequency variation in order to improve bus voltage and frequency regulation with effective power sharing for intermittent sources. The operation of the islanded hybrid ac/dc microgrid is performed with solar, wind, and energy storage system under variable generation and load conditions. In order to make robustness of the system, there are considered different cases for generation and load scenarios. In the transient state, the overshoot and settling time of frequency and voltage are improved, as well as the frequency and voltage regulations are found within the permissible limit in the steady state. Furthermore, the corresponding variations are shown in tabular form in the simulation result. The actual data of solar irradiance and wind speed have been taken from the National Renewable Energy Laboratory. The performance of the system is verified in MATLAB/Simulink environment.
G. S. Kumar, G. Mamatha,
Volume 19, Issue 1 (March 2023)
Abstract
In today's technological environment, designing the Static Random Access Memory (SRAM) is most vital and critical memory devices. In this manuscript, two kinds of 5TSRAM are designed using different CNTFET such as Dual-ChiralityGate all around (GAA) CNTFET and Ballistic wrap gate CNTFET based 5T SRAM cell designs for enhancing the read/write assist process. Here, the proposed Dual-ChiralityGAA-CNTFET based 5T-SRAM has two cross-coupled inverters using one access transistor that is connected to the bit line (BL) and word line (WL) through minimum supply voltage. Instead of cross-coupled inverter circuit, the BWG-CNTFET based 5T-SRAM cell is intended for achieving less power and improved read/write assist process. Also, one transistor is executed as low-threshold (LVT) device in the proposed BWG-CNTFET based 5T-SRAM. Thus, proposed two kinds of 5T SRAM cells increases the read/write assist operation and reduce the leakage current/ power. The simulation of the proposed two kinds of 5T SRAM cell is done by HSPICE simulation tool and the performance metrics are calculated. Therefore, the proposed Dual-ChiralityGAA-CNTFET based 5T-SRAM cell design has attained 11.31%, 51.47% lower read delay, 44.44%, 26.33% lower write delay, 36.12%, 45.28% lower read power, 34.5% , 22.41% lower write power, 37.4%, 15.3% higher read SNM and 35.8%, 12.09% higher write SNM than Double gate carbon nanotube field effect transistors (DG CNTFET) and state-of-art method respectively. Similarly, the proposed BWG-CNTFET 5T SRAM cell design has attained 45.53%, 38.77% lower write delay, 56.67%, 45.64% lower read delay, 58.4%, 56.75% lower read power, 49.66%, 28.56% lower write power, 35.32%, 12.7% higher read SNM and 45.8%, 15.6% higher write SNM than Reduced Power with Enhanced Speed (RPES) approach and state-of-art method respectively.
Jayati Vaish, Anil Kumar Tiwari, Seethalekshmi K.,
Volume 19, Issue 4 (December 2023)
Abstract
In recent years, Microgrids in integration with Distributed Energy Resources (DERs) are playing as one of the key models for resolving the current energy problem by offering sustainable and clean electricity. Selecting the best DER cost and corresponding energy storage size is essential for the reliable, cost-effective, and efficient operation of the electric power system. In this paper, the real-time load data of Bengaluru city (Karnataka, India) for different seasons is taken for optimization of a grid-connected DERs-based Microgrid system. This paper presents an optimal sizing of the battery, minimum operating cost and, reduction in battery charging cost to meet the overall load demand. The optimization and analysis are done using meta-heuristic, Artificial Intelligence (AI), and Ensemble Learning-based techniques such as Particle Swarm Optimization (PSO), Artificial Neural Network (ANN), and Random Forest (RF) model for different seasons i.e., winter, spring & autumn, summer and monsoon considering three different cases. The outcome shows that the ensemble learning-based Random Forest (RF) model gives maximum savings as compared to other optimization techniques.
Chhaya Belwal, Kunwar Singh, Shireesh Kumar Rai,
Volume 20, Issue 2 (June 2024)
Abstract
This paper introduces a floating flux-controlled meminductor emulator, implemented using two voltage differencing differential difference amplifier (VDDDA) along with a memristor and capacitor. Grounded and floating configurations are simulated with TSMC 0.18 µm level-49 BSIM3 CMOS process parameters in LTspice, showcasing the performance of the proposed circuits. The circuit features electronic tunability, allowing for the adjustment of nonlinear flux through the tuning of bias voltage. Simulation results validate the frequency-dependent current-flux dynamics of the proposed meminductor emulator. The simulation results, which involve frequency-dependent pinched hysteresis loops, transient analysis, non-volatility, and Monte Carlo analysis of the proposed meminductor, affirm the functionality and adequacy of the proposed design. A Chua’s oscillator is realized using proposed VDDDA-based meminductor as non-linear element.
Kavitha Manickam, P.k. Janani, S. Karthick, S. Arulsivam, C. Vikram, G. Hariharan, R. Kavinkumar, P. Ganesh,
Volume 20, Issue 2 (June 2024)
Abstract
The overall performance of any integrated circuit is defined by its proper memory design, as it is a mandatory and major block which requires more area and power. The prime interest of this article is to design a memory structure which is tolerant to variations in CNFET (Carbon nanotube field effect transistor) parameters like pitch, diameter and number of CNT tubes, and also offer low power and high speed of operation. In this context, CNFET based stacked SRAM (Static random access memory) design is proposed to attain the above mentioned criteria. Concept of stack effect is utilized in the cross coupled inverter section of the memory structure to attain low power. The power, speed and energy analysis for the proposed structure is done, and compared with the conventional structures to justify the proposed memory cell performance. HSPICE simulation results has confirmed that the proposed structure offers about 34%, 54% and 95% power saving in hold mode, read mode and write mode respectively. In speed and energy point of view it provides about 97% read delay, 92% write delay and 98% energy savings than the conventional memory structures. These results make it clear that the proposed SRAM is suitable for the 5G networks where circuit speed, power and energy consumption are the major concern.
