P. Gupta, S. K. Jana,
Volume 17, Issue 2 (June 2021)
Abstract
The advancement in the integrated circuit design has developed the demand for low voltage portable analog devices in the market. This demand has increased the requirement of the low-power RF transceiver. A low-power phase lock loop (PLL) is always desirable to fulfill the need for a low power RF transceiver. This paper deals with the designing of the low power transconductance- capacitance (Gm-C) based loop filter with the help of the gate-driven quasi bloating Bulk (GD-QFB) MOS technique. The GD-QFB MOS-based operational transconductance amplifier (OTA) has been proposed with a high dc gain of 82.41 dB and less power consumption of 188.72 µW. Further, Gm-C based active filter has been designed with the help of the proposed GD-QFB OTA. The simulation results of Gm-C filter attain a -3 dB cut-off frequency of 59.08 MHz and power consumption of 188.31µW at the supply voltage of 1V. The proposed Gm-C filter is suitable for the designing of 1-3 GHz low power PLL.
Pravat Biswal, Veera Venkata Subrahmanya Kumar Bhajana, Pavel Drabek,
Volume 18, Issue 4 (December 2022)
Abstract
This paper proposes two new soft-switching transformerless converters with high voltage conversion ratio. These proposed converters achieve soft-switching each with a single auxiliary resonant cell. The merit of these converters is reduced switching losses with lesser number of devices. The main switching devices are turned off with zero current switching (ZCS). Apart from the soft-switching feature, the voltage conversion ratio is increased in comparison with the existing topologies. The operating principles and the simulation results on 12V/200V/500W converter system are presented in this paper.
Kavitha Manickam, P.k. Janani, S. Karthick, S. Arulsivam, C. Vikram, G. Hariharan, R. Kavinkumar, P. Ganesh,
Volume 20, Issue 2 (June 2024)
Abstract
The overall performance of any integrated circuit is defined by its proper memory design, as it is a mandatory and major block which requires more area and power. The prime interest of this article is to design a memory structure which is tolerant to variations in CNFET (Carbon nanotube field effect transistor) parameters like pitch, diameter and number of CNT tubes, and also offer low power and high speed of operation. In this context, CNFET based stacked SRAM (Static random access memory) design is proposed to attain the above mentioned criteria. Concept of stack effect is utilized in the cross coupled inverter section of the memory structure to attain low power. The power, speed and energy analysis for the proposed structure is done, and compared with the conventional structures to justify the proposed memory cell performance. HSPICE simulation results has confirmed that the proposed structure offers about 34%, 54% and 95% power saving in hold mode, read mode and write mode respectively. In speed and energy point of view it provides about 97% read delay, 92% write delay and 98% energy savings than the conventional memory structures. These results make it clear that the proposed SRAM is suitable for the 5G networks where circuit speed, power and energy consumption are the major concern.
