Showing 4 results for Faraji Baghtash
H. Faraji Baghtash, S. J. Azhari, Kh. Monfaredi,
Volume 7, Issue 4 (December 2011)
Abstract
In this paper a novel very high performance current mirror is presented. It favorably benefits from such excellent parameters as: Ultra high output resistance (36.9GΩ), extremely low input resistance (0.0058Ω), low output (~0.18V) and low input voltage (~0.18V) operation, very low power consumption (20μW), very low offset current (1pA), ultra wide current dynamic range (150dB), and ultra high accuracy (error = 0.003%). The circuit has a very simple compact architecture and uses a single 1V power supply. The qualitative performance of the circuit is validated with HSPICE simulations using HSPICE TSMC 0.18μm CMOS technology.
T. Azadmousavi, H. Faraji Baghtash, E. Najafi Aghdam,
Volume 14, Issue 2 (June 2018)
Abstract
This work introduces a new and simple method for adjusting the gain of current mirror. The major advantage of the proposed architecture is that, unlike the conventional variable gain current mirror, it does not need the change of the biasing current to adjust current gain. Therefore, the power dissipation remains constant in all of the gain settings. In addition, the proposed variable gain current mirror have linear-in-dB gain control characteristic, simple structure, and small occupied area. The gain of the current mirror can be simply varied from 1.3dB to 21dB while the 3-dB bandwidth of the circuit remains around 12.3MHz or 33.6MHz at operation frequency range of 1.9MHz-14.2MHz and 6.6MHz-40.2MHz respectively. The proposed circuit draws negligible power of 6.9µW from 1.8V supply voltage. The simulation results of designed variable gain current mirror in 0.18μm standard CMOS technology confirms the effectiveness of the proposed circuit.
T. Azadmousavi, H. Faraji Baghtash, E. Najafi Aghdam,
Volume 15, Issue 2 (June 2019)
Abstract
A power efficient gain adjustment technique is described to realize programmable gain current mirror. The dissipation power changes over the wide gain range of structure are almost negligible. This property is in fact very interesting from power management perspective, especially in analog designs. The simple structure and constant frequency bandwidth are other ever-interesting merits of proposed structure. The programming gain range of structure is from zero up to 18dB under operating frequency range from 72 kHz to 173 MHz. The maximum power dissipation of designed circuit is only 3.1 µW which is drawn from 0.7 V supply voltage. Simulation results in 0.18 µm CMOS TSMC standard technology demonstrate the high performance of the proposed structure.
H. Faraji Baghtash, Kh. Monfaredi,
Volume 15, Issue 3 (September 2019)
Abstract
A novel active feedback frequency compensation scheme is presented in this work. Based on the proposed technique, an amplifier with two main poles in its frequency bandwidth can be easily compensated by introducing a pole-zero pair in a local feedback. The proposed method is mathematically analyzed and then based on the derived formulations, a design procedure is established. The capability of the proposed technique is examined considering a well-known two-stage amplifier, considering just a trivial modification on its input stage. To gain an analogous and fair insight, the performance of the proposed structure is compared with that is of the optimally designed miller-compensated two-stage amplifier. The post-layout simulations are accomplished with TSMC 180nm CMOS standard technology. The Spectre post-layout simulations show that the proposed structure outperforms the traditional structure in terms of power consumption and gain bandwidth product. The robustness of the design is checked with Monte Carlo simulations.