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S. R. Talebiyan, S. Hosseini-Khayat,
Volume 5, Issue 3 (9-2009)

A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.
F. Mohseni-Kolagar, H. Miar-Naimi,
Volume 7, Issue 3 (9-2011)

Due to the nonlinear nature of the Bang-Bang phase-locked loops (BBPLLs), its transient analysis is very difficult. In this paper, new equations are proposed for expression of transient behavior of the second order BBPLLs to phase step input. This approach gives new insights into the transient behavior of BBPLLs. Approximating transient response to reasonable specific waveform the loop transient time characteristics such as locking time, peak time, rise time and over shoot are derived with acceptable accuracy. The validity of the resulted equations is verified through simulations using MATLAB SIMULINK. Simulation results show the high accuracy of the proposed method to model BBPLLs behavior.
R. Mirzalou, A. Nabavi, Gh. Darvish,
Volume 8, Issue 3 (9-2012)

This paper presents a new ultra-wideband LNA which employs the complementary derivative superposition method in noise cancellation structure. A pMOS transistor in weak inversion region is employed for simultaneous second- and third-order distortion cancellation. Source-degeneration technique and two shunt inductors are added to improve the performance at high frequencies. The degeneration inductor resonates at fT/2 and realizes a new input matching technique that widens the bandwidth with decreasing its quality factor and input capacitance, while flattens the input resistance and also improves the 1dB Compression Point. The shunt inductors resonate at the center frequency of the band and improve the effective bandwidth of noise/distortion cancellation technique. This LNA has been designed in a 0.18-μm CMOS process and consumes 8.3 mA from 1.8 V power supply. The chip area is 0.55mm2. The noise figure and voltage gain are 4.48-5.18 dB and 13 dB, respectively. S11 is lower than -13.5 dB over 5.8–10.6 GHz and IIP3 is 14.5–17.5 dBm, IIP2 is 14–15.5 dBm. This technique improves IIP3 more than 9dB.
A Ghorbani-Nejad, A Jannesari,
Volume 9, Issue 4 (12-2013)

A two stage sub-µW Inverter-based switched-capacitor amplifier-filter is presented which is capable of amplifying both spikes and local field potentials (LFP) signals. Here we employ a switched capacitor technique for frequency tuning and reducing of 1/f noise of two stages. The reduction of power consumption is very necessary for neural recording devices however, in switched capacitor (SC) circuits OTA is a major building block that consumes most of the power. Therefore an OTA-less technique utilizing a class-C inverter is employed that significantly reduces the power consumption. A detailed analysis of noise performance for the inverter-based SC circuits is presented. A mathematical model useful for analysis of such SC integrators is derived and a good comparison is obtained between simulation and analytical technique. With a supply voltage of 0.7V and using 0.18 µm CMOS technology, this design can achieves a power consumption of about 538 nW. The designed amplifier-filter has the gains 18.6 dB and 28.2 dB for low pass only and cascaded filter, respectively. By applying different sampling frequencies, the filter attains a reconfigurable bandwidth.
M. Ashraf,
Volume 14, Issue 2 (6-2018)

This work studies the effects of dynamic threshold design techniques on the speed and power of digital circuits. A new dynamic threshold transistor structure has been proposed to improve performances of digital circuits. The proposed switched-capacitor dynamic threshold PMOS (SC-DTPMOS) scheme employs a capacitor along with an NMOS switch in order to effectively reduce the threshold voltage of a PMOS transistor. The proposed structure improves the propagation delay of a circuit and is much suitable for those circuits with high switching factor. Post layout simulation results using TSMC 180 nm CMOS technology at 0.2V supply voltage shows 45% improvement in delay as well as 25% less power consumption at the cost of only 53% more occupied area.

S. J. Azhari, M. Zareie,
Volume 15, Issue 2 (6-2019)

In this paper, a novel low voltage low power current buffer was presented. The proposed structure was implemented in CMOS technology and is the second generation of OCB (orderly current buffer) called OCBII. This generation is arranged in single input-single output configuration and has modular structure. It is theoretically analyzed and the formulae of its most important parameters are derived. Pre and Post-layout plus Monte Carlo simulations were performed under ±0.75 V by Cadence using TSMC 0.18 µm CMOS technology parameters up to 3rd order. The proposed structure could expand and act as a dual output buffer in which the second output shows extremely high impedance because of its cascode configuration. The results prove that OCBII makes it possible to achieve very low values of input impedance under low supply voltages and low power dissipation. The most important parameters of 1st, 2nd and 3rd orders, i.e. input impedance (Rin), -3 dB bandwidth (BW), power dissipation (Pd) and output impedance (Ro) were found respectively in Pre-layout plus Monte Carlo results as:
1st order: Rin (52.4 Ω), BW (733.7 MHz), Pd (225.6 µW), Ro (105.6 kΩ)
2nd order: Rin (3.8 Ω), BW (576.4 MHz), Pd (307 µW), Ro (106.4 kΩ)
3rd order: Rin (0.34 Ω), BW (566.9 MHz), Pd (535.6 µW), Ro (118.2 kΩ)
And in Post-layout plus Monte Carlo results as:
1st order: Rin (59.9 Ω), BW (609.6 MHz), Pd (212.4 µW), Ro (106.9 kΩ)
2nd order: Rin (11.3 Ω), BW (529.3 MHz), Pd (389.9 µW), Ro (109.8 kΩ)
3rd order: Rin (5.8 Ω), BW (526.5 MHz), Pd (514.5 µW), Ro (125.5 kΩ)
Corner cases simulation results are also provided indicating well PVT insensitivity advantage of the block.

N. Sayyadi Shahraki, S. H. Zahiri,
Volume 16, Issue 2 (6-2020)

In this paper, we propose an efficient approach to design optimization of analog circuits that is based on the reinforcement learning method. In this work, Multi-Objective Learning Automata (MOLA) is used to design a two-stage CMOS operational amplifier (op-amp) in 0.25μm technology. The aim is optimizing power consumption and area so as to achieve minimum Total Optimality Index (TOI), as a new and comprehensive proposed criterion, and also meet different design specifications such as DC gain, Gain-Band Width product (GBW), Phase Margin (PM), Slew Rate (SR), Common Mode Rejection Ratio (CMRR), Power Supply Rejection Ratio (PSRR), etc. The proposed MOLA contains several automata and each automaton is responsible for searching one dimension. The workability of the proposed approach is evaluated in comparison with the most well-known category of intelligent meta-heuristic Multi-Objective Optimization (MOO) methods such as Particle Swarm Optimization (PSO), Inclined Planes system Optimization (IPO), Gray Wolf Optimization (GWO) and Non-dominated Sorting Genetic Algorithm II (NSGA-II). The performance of the proposed MOLA is demonstrated in finding optimal Pareto fronts with two criteria Overall Non-dominated Vector Generation (ONVG) and Spacing (SP). In simulations, for the desired application, it has been shown through Computer-Aided Design (CAD) tool that MOLA-based solutions produce better results.

A. Rahali, K. El Khadiri, A. Tahiri,
Volume 19, Issue 1 (3-2023)

In this paper, a Li-Ion Battery Charger Interface (BCI) circuit with fast and safe charging for portable electronic devices is proposed. During the charging of Li-Ion battery, current spikes due to asynchronous control signals, and temperature are factors that greatly affect battery performances and life. This circuit has the following features: prevents current spikes and also incorporates a permanent battery temperature monitoring block. The BCI uses a dual current source and generates a constant current in a large current mode of 1.5 A, further reducing charging time. The proposed BCI was designed and simulated in Cadence Virtuoso using TSMC 180 nm technology. The simulation results of the control signals show that the proposed architecture was able to eliminate the current drifts and keep the battery temperature within the normal operating range.

Pampa Debnath, Diptadip Barai, Rajorshi Mandal, Ayeshee Sinha, Jeet Saha, Arpan Deyasi,
Volume 20, Issue 2 (6-2024)

A novel architecture is proposed in the present paper for detection and monitoring of air pollution at real-time condition following industrial standard, embedded with gas sensors which are able to identify both organic as well as inorganic hazardous contents. A vis-à-vis comparative analysis is carried out with existing literature highlighting cons of most referred circuits, both in component, system and power consumption levels, and a generalized drawback is reported citing their inefficacy for real-time data collection and accuracy level. Detailed review is reported based on qualitative assessments also, and henceforth, justifies the significance of the proposed design; where not only higher ranges of detection are possible, however is also associated with lower power consumption (26.41% and 10.71% respectively compared to the two latest circuits) and finer detection of dust particles even at extremely low concentration. The architecture will help to implicate precautionary steps at real-time condition for controlling the harmful effect in Society.

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© 2022 by the authors. Licensee IUST, Tehran, Iran. This is an open access journal distributed under the terms and conditions of the Creative Commons Attribution-NonCommercial 4.0 International (CC BY-NC 4.0) license.