Volume 17, Issue 3 (September 2021)
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- Proposing a new analog neuromorphic circuit to implement the effect of astrocyte in desynchronization of the neural network;
- Proposing a population of twenty neurons is synchronized with the same input currents;
- By involving the astrocyte feedback circuit, the synchronization of the neural network is disturbed;
- The proposed circuit is designed and simulated using HSPICE simulator in 0.35μm standard CMOS technology.
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- Proposing an intelligent state estimator based on adaptive neuro-fuzzy inference system;
- Comparing the accuracy of the presented estimator by ANN and WLS;
- Analyzing the capability of the method to detect and correct the injected false data;
- Considering the probability of load variation as a practical condition in power system.
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- Study of gate delay changes on altering the viability of circuit paths.
- Proposing a complete path-based algorithm of gate resizing which utilizes viability analysis in the selection of candidate nodes.
- Decreasing the size of all circuit gates at the beginning of the proposed method and then increasing the size of circuit gates which violate the circuit timing constraint, instead of using gate slacks.
- Introducing an incremental algorithm for gate resizing which uses previously-obtained not-altered viabilities of circuit paths.
- Proposing a proper metric, based on viability conditions, to select the best nodes to become a candidate for resizing.
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- The combined model of generation expansion planning considering small signal stability performance of power system is presented.
- A multi-objective representative of the problem is considered and that is solved with ANSGM-III.
- The role of WAS and delay of wide-area signals in GEP is evaluated with multiple scenarios.
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- The original contribution of this paper is the application of the artificial neural networks (ANN) in the space vector pulse width modulation (SVPWM) and experimental investigation of this novel method.
- A SVPWM method based on ANN controller is developed for two-level inverter and compared with conventional SVPWM strategy. On the other hand, the proposed technique is compared to pulse width modulation (PWM).
- The proposed SVPWM method minimized the total harmonic distortion (THD) compared to the SVPWM and PWM.
- The proposed technique is simple and easy to implement.
- The proposed method is robust compared to traditional SVPWM and PWM techniques.
- In this paper, we propose a new SVPWM technique of VSI.
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- A three-phase dual-port T-type Asymmetrical multilevel inverter (DP-ASMLI) using two sources, high voltage level from solar and the battery forming the low voltage level is considered for grid interconnection.
- The system performs a transformerless operation for grid interconnection of 100kW range.
- A vertical shifted SPWM is used for the ASMLI circuit. A closed-loop control using PQ theory is implemented for obtaining power balance at 0.7 modulation index.
- Design of front end converter, inverter, and the filter parameters are addressed.
- The THD of the current harmonics present in the system is 0.01% and voltage harmonics is 0.029% which is well within the permissible limits of IEEE-519 standard.
- A comparison of THD’s, voltage, current stresses on the switches, and conduction losses are presented for a single-phase system w. r. t. a two-level inverter which shows improved efficiency and low THD for use in grid interconnection with renewable energy sources.
- The power balance between the inverter to load and the grid for load sharing is efficient.
- It is observed that the T-type inverter is a better replacement for the conventional H-bridge inverter for grid interconnection.
- The work can be extended with other renewable energy sources with different control algorithms. The DC-DC converters of the latest methodology (sepic/interleaved boost) also can be included.
- The battery charge controller can be understood with the latest algorithms.
- This inverter finds application in back-back inter tie, induction heating, Reactive power compensation, adjustable speed drives, UPS, etc.
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- FPGA implementation of low power true random number generator through ring oscillator for IoT applications and smart cards is presented.
- Ring oscillators based on higher jitter and sampling techniques are exploited to present true random number generator.
- Further statistical parameters of the generated data stream are enhanced through post processing technique.
- The presented true random number generator technique does not depend on the characteristics of a particular FPGA.
- The presented technique consumes low power, requires low hardware footprints, and passes the entire NIST statistical test suite.
- True random number generator with enhanced security through post-processing may be applied for encryption/decryption of data in smart cards and IoT.
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- A new approach is presented to model the correlation between wind power and load.
- Using a combined k-means–PSO approach to achieve an optimum number of data clusters.
- The uncertainty of wind power and load demand is modeled by creating less, but closer to real scenarios.
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- Proposing proposes a two-stage islanding detection method for power systems equipped with multiple-DGs through estimation of high frequency impedance and determination of the total harmonic distortion;
- Estimating impedances of the DGs at distinct frequencies to avoid interval overlaps;
- Applying decentralized injections with separate frequency bands;
- Distinguishing islanding from other power system ordinary transient events.
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- Up to now, most control methods used for CDFIGs are based on voltage oriented control, and the nonlinear control method is not proposed for them.
- The effectiveness of the proposed method in different scenarios such as feeding unknown, nonlinear and harmonic distorted loads is verified. As well, the effect of variable wind or prime mover’s speed on the output voltage is compared with three control methods.
- In order to present a clear comparison between the proposed method and some recent methods, we compare three methods with simulation and experimental tests: VOC, SMC, and TSMC.
- The state-space equation of CDFIG has 6 states. Using SMC and TSMC control, we use only the output variables of CDFIG, which feeds an isolated load and the output voltage control with constant and step-changed references is verified.
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Abstract
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Highlights
- IMEC considers all components of air-gap permeance.
- IMEC gets help from CMs for calculating air-gap permeance components.
- CM method can accurately take into account the air-gap region.
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Highlights
- High performance sub-volt current mirror are widely used in building mixed-mode low power VLSI systems.
- Current mirror designs based on flipped voltage follower can work at low supply voltage.
- Modification is carried in conventional flipped voltage follower structure which resulted in low impedance nodes which here is utilized as an input.
- Design of a current mirror using modified flipped voltage follower structure results in improved bandwidth and reduced input resistance without affecting other parameters.
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