Volume 17, Issue 2 (June 2021)                   IJEEE 2021, 17(2): 1872-1872 | Back to browse issues page

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Abstract:   (2422 Views)
The advancement in the integrated circuit design has developed the demand for low voltage portable analog devices in the market. This demand has increased the requirement of the low-power RF transceiver. A low-power phase lock loop (PLL) is always desirable to fulfill the need for a low power RF transceiver. This paper deals with the designing of the low power transconductance- capacitance (Gm-C) based loop filter with the help of the gate-driven quasi bloating Bulk (GD-QFB) MOS technique. The GD-QFB MOS-based operational transconductance amplifier (OTA) has been proposed with a high dc gain of 82.41 dB and less power consumption of 188.72 µW. Further, Gm-C based active filter has been designed with the help of the proposed GD-QFB OTA. The simulation results of Gm-C filter attain a -3 dB cut-off frequency of 59.08 MHz and power consumption of 188.31µW at the supply voltage of 1V. The proposed Gm-C filter is suitable for the designing of 1-3 GHz low power PLL.
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  • The Major contribution of the work includes the design of GD-QFB OTA and its uses in GD-QFB MOS based Gm-C filter. GD-QFB MOS technique is a good low power design technique.
  • In this paper, GD-QFB MOS differential input two-stage OTA has been presented. The simulation results show the significant improvement in DC gain, CMRR, and reduction in the power consumption of OTA.
  • Further, the proposed OTA is used in the design of the tunable Gm-C filter for low power PLL applications in the range of 1-3 GHz.

Type of Study: Research Paper | Subject: Analog Circuits
Received: 2020/05/02 | Revised: 2020/07/05 | Accepted: 2020/07/06

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